Continuous metallized regenerated cellulose fibers for advanced applications (e.g. multi-functional composites) are produced by electroless copper plating. Copper is successfully deposited on the surface of cellulose fibers using commercial cyanide-free electroless copper plating package commonly available for manufacturing of printed wiring boards. The deposited copper is found to enhance the thermal stability, electrical conductivity and resistance to moisture uptake of the fibers. On the other hand, involved chemistry results in altering the molecular structure of the fibers as is indicated by the degradation of their mechanical performance (tensile strength and modulus).

This work investigates the capability of drilling and metallization of microvias of diameter less than 10 µm with aspect ratios of 1-10, using a fully additive process.

The microvia has been produced using a sequential build up layer of urethane through which the via has been produced. The urethane layer is applied using spin-coating. Current process setting produces a 15 µm layer thickness. For thicker urethane, multiple layers are applied. Drilling of the via-hole through is made using 266 nm UV laser.

The metallisation of the via-hole was made using a process called Covalent Bonded Metallisation (CBM). This process modifies the urethane surface by a grafting process where polymers are covalently bonded to the surface where metallisation is desired. A roughly 5 µm thin film of the used grafting solution is applied to the substrate surface. The grafting process is initiated by laser which draws the patterns where copper is desired.

After laser drawing, the substrate is cleaned with deionized water. Next, the substrate is through a commercialchemical-copper process which builds copper only at the laser initiated patterns. Copper thicknesses of 1 µm is easily achievable. To increase the copper thickness, the substrate may be run into thick building chemical-copper process to achieve thicknesses up to 8 µm.

This paper introduces a practical test method that combines statistics with the contactless test approach. Experiments using real conventional PCBAs have shown the effectiveness of the method, where significant z-scores are obtained to discriminate defective interconnects. The studied test cases involve conventional Printed Circuit Board Assemblies (PCBAs) with open sockets and Ball Grid Array (BGA) packages.

State-of-the-art printed circuit boards (PCBs) have become extremely dense and are not fully accessible for applying physical testing solutions. Extra steps are required in the design and manufacturing process for testing advanced printed wiring boards (PWBs) with embedded passive components. This processing is further complicated by upcoming sequential build-up (SBU) technologies that provide feature sizes smaller than 10 $\mu$m and that do not allow physical access for testing the interconnect between two pads. In this paper, we propose a new contactless technique for overcoming the SBU challenge for testing interconnects between embedded components. A test trace is employed as a sensor, which senses the terminations of the trace being tested. The simulation and analysis results of this study demonstrate the feasibility of this concept for application to SBU and conventional PCB/PWB interconnect testing to overcome the barriers to physical access. Robustness of the approach has been studied against packaging deviations and possible testing process variations. To ensure defect detection with feasible margins, design for testability (DfT) rules have been established for practical PCB dimensions.

Electronics are still continuing to respond to the small-feature size requirement for economical, performance and environmental benefits.Due to the non-idealities in the manufacturing process of circuit boards, electronics production yield is never 100 %. To maintain a good reputation of a product brand, testing of circuit boards is highly recommended before shipping to the customer.Because of the strive for high density electronics, an increasing percentage of circuit boards will not be accessible for the current test approaches. New technologies as High-Density Interconnect (HDI), Through-Silicon Via (TSV), embedded chips and Sequential Build-Up (SBU) circuit boards will even further increase the challenge for the test business. Current test approaches to dense circuit boards most often require extra test pads and thus additional cost and size. Already the use of today's standard Ball Grid Array (BGA) packages has introduced difficulties to conventional Printed Circuit Boards (PCBs) testing. To deal with these challenges on testing and to enhance the current test methodologies, this thesis addresses improvements to the existing test methodologies and also proposes test approaches usable in conjunction with Sequential Build-Up (SBU) production of circuit boards.Firstly, this thesis introduces a new indirect method to test Printed Wiring Board (PWB)/PCB where probing is feasible. A Radio Frequency (RF) signal is injected into the trace under test, instead of a DC current. The phase shift between the incident and the reflected signals is measured as it carries information about the Unit Under Test (UUT). The solution implies faster and lower probing technology resources as it is possible to test against opens and shorts in one pass, it uses a single probe. Based on several cases, manufacturing defects are discriminated with significant margins.Secondly, a contactless approach for testing PCB is proposed for interconnects where probing is not feasible. A test trace is employed on another test board as a sensor, which reads the terminations of the trace of the UUT. The results have shown the feasibility of this concept to be applied to the state of the art HDI and to conventional PCBs with hidden interconnects. Design for Testability (DfT) rules have been created for robust error detection that allow fault detection in the range of a few Parts per Billion (PPB) while accounting for component specification variabilities of 10 - 20 %. It has been shown that the maximum test frequency is around 6 GHz, which is manageable.

It is believed that data-stream-driven computing is power and energy efficient as compared to its counterpart, instruction-stream-driven computing. This latter requires memory access and memory control overheads while the processor is fetching task instructions from the memory. The programmer describes all the tasks as instructions in the program memory. On the other hand data-stream-driven computer is already configured or hardwired for a specific computing operation, no memory is required apart from data storage. In some contexts we refer to data-stream-driven computers as accelerators or single-purpose processors. This chapter discusses the benefit of data-stream-driven computing for better power and energy efficiency. We took matrix multiplication as an example application to compare the power and energy dissipations between load/store and non-instruction fetch-based architectures. We witnessed that single-purpose processor reduces almost 100% of the dynamic power when replacing the general-purpose processor. With the current mainstream transistor technology, morphware platforms that allow massive parallelism are the potential key for data-stream-driven computer implementations to saving energy in battery-powered embedded systems and to solve the dissipated power dilemma, as the heat becomes the bottleneck of traditional high frequency processors. If the same strategy is applied to mainstream computers and data center servers, we will not only reduce electricity bills but we will also contribute to greener computing by lowering the IT sector’s CO2 emissions.

Signal integrity becomes more important when the length of the Printed Wiring Board (PWB) traces surpasses lambda/10 where lambda where denotes the wavelength. For fast digital communication purpose and low energy consumption in CMOS technology, faster rise time of the clock which means higher harmonic frequency, has always been preferable. In this case, the importance of considering signal integrity gets a higher priority as issues such reflections and crosstalk between adjacent traces cannot be omitted, especially in dense High Density Interconnect (HDI) boards. Several factors control the effect of reflections and the crosstalk such as the shape and dimension of the traces, the isolator characteristics which is inserted between the trace and the ground plane, the nearness and the geometry of the nearby conductors. In other words, these factors control the characteristic impedance of the traces and the mutual inductances and capacitances between the adjacent traces. Although these factors have been taken into account during the design phase for good signal integrity, the manufacturing process, which differs from vendor to vendor, has a great impact on the above factors. PWB manufacturing process may result in many different variations, which involve the dielectric constant, the thickness of the insulator, the trace width and the copper foil thickness. In addition to these variations, the etching quality that falls mainly in three different categories of trapezoidal trace form. In this paper we present the effect of three different etching shapes on the characteristic impedance. Moreover, it is concluded that one could gain space which can be used for shrinking the electronics and/or saving the raw material when trading the characteristic impedance error for space. Similar method is followed to investigate the crosstalk reduction between two adjacent microstriplines when tolerating the error in the characteristic impedance. This procedure can only be applied when a 90 degree angle process is feasible.

This paper demonstrates statistically the impact of PCB manufacturing variations on the characteristic impedance. Moreover, it shows that the characteristics of the PCBs vary across different suppliers. These differences cannot be tolerated in some applications where the characteristic impedance is restricted to be within a specific range. We sampled 3 x 20 PCBs, each batch of twenty is ordered from a different manufacturer: The sampling consisted of measuring the phase shift between the reflected and the incident signals when injecting a ISO MHz sinewave into a PCB trace. The trace is selected to be the same for all samples. All the PCBs are ordered to be identical and designed for 50 devices. Our conclusion was drawn after running the T-tests to assess statistically the significance of the difference occurring between the PCBs. Based on the computed P-values all three batches are different from each other in the mean of the measured phase shift with 95 % confidence. The difference between the measured and the expected characteristic impedance is found as 3 %, 10 % and 20 %for these three manufacturers. We also witnessed board- to-board variations even within the same batch and from the same supplier due to the process instability by looking at the probability density of having the same phase shift that is equal to the mean. Some samples showed 2.6 % to 3.5 % difference above the mean.

Printed Wiring Board (PWB) and Printed Circuit Board Assembly (PCBA) testing aims to ensure an error free board after the etching and the assembly processes. After the etching process, several types of errors might occur such as opens and bridges, which are already, showstoppers in Direct Current (DC) applications. Mouse bites, spurs and others such as weak traces, which can be problematic in Radio Frequency (RF) and high-speed signals applications. Loading expensive component on defective boards can be economically catastrophic especially for high volume production. The rule of ten which has been reported by the production experts says that the defect costs ten times when detected in the next testing phase. Bare board also needs to be tested for the characteristic impedance correctness due to the process variations and the compounding raw material tolerances that can cause characteristic impedance mismatches. Although testing the characteristic impedance is not in interest in some application, sampling the characteristic impedance for a specific design is one way to test the manufacturing process stability for better tuning, otherwise PWBs might differ from each other even within the same batch. In addition to the possibility of defective PWB, the assembly process is never perfect to achieve 100 % of PCBA yield due to the possible errors in the process steps such as paste application, pick and place operations and soldering process which might lead to bridges, opens, wrong or miss oriented components.For low volume production, flying probes test technology is cost efficient as compared to bed-of-nails. The performance of the flying probes system depends on the test algorithm, the mechanical speed and the number of probes. To reduce the initial and maintenance costs of the probing technology and to accelerate the test time, Paper A introduces a new indirect method to test PWB continuity and isolation testing using a single probe for testing both continuity and isolation at the same time. RF signal is injected into the trace under test, instead of a DC current. The phase shift between the incident and the reflected signals is measured as it carries the information about the correctness of the trace when compared with a reference value of the same trace in the correct board. The method shown an important capability for detecting PWB defects such as as opens, DC and RF bridges, exceeded and different width lines. The margin in the measurement between a defective and a correct board, which depends on the type of the defect, is about 7 % to 68 %. Applying this approach to PCBA testing led to significant margins between correct and defective interconnect. The test cases in paper C shown 40 % and 33 %. Moreover, this margin has been proven to be important even for short microstrip line, which intended to connect two typical IC pins. This technique is strongly recommended to be applied to PCBA testing where probing is feasible. The approach can be applied to the complete layout testing or to boost a test strategy whose test solutions are not covering 100 % of the possible defects.By applying this test solution to bed-of-nails equipment, 50 % of the probes will be reduced, on the other hand, for a given design with NI isolated traces and NA adjacent pairs, employing this solution to flying probes system with two probes, leads to the reduction of the number of tests from (NI+NA) tests to NI tests as isolation and continuity are performed in one go. Flying probes system involves mechanical movements, which dominate the test time, reducing the number of the mechanical movements increases dramatically the test throughput. On the other hand, this method is believed to be extremely fast to test the correctness of the characteristic impedance which is prone to variations due to the instability of the PWB manufacturing process, in the same time one could employ the method to evaluate the process stability by checking after each batch of PWBs. Paper B and D provide insight into the impact of the PWB manufacturing variations on the characteristic impedance. Moreover single probe approach is believed to have a good potential for Sequential Build-Up (SBU) interconnects testing where connections between component pads and the upper layers are often impossible to test with the current test technologies.

Printed wiring board (PWB) and printed circuit board assembly (PCBA) testing is part of the electronics production, which has a great impact on the profitability. Always high throughput and low cost testing is needed but for high quality and reliability. Bare board testing is vital before components loading. Defects after the PWB manufacturing process are possible such as opens, bridges, near-opens, near-bridges and characteristic impedance mismatches due to process variations and compounding raw material tolerances. Moreover, defects might cost about ten times when detected in the next test phase, another motivation for unpopulated board test is loading expensive components on a set of defective boards might be economically catastrophic. Flying probe systems, which were developed in late 1980’s, are commonly used and favorable to perform bare board isolation and continuity testing, especially when the volume is not big enough to justify bed of nails purchase. Flying probe system performance for a given bare board depends on the test algorithm, the mechanical speed and the number of probes. To reduce the cost on expensive test probes and probe maintenance and to accelerate the test time, this paper presents a new and cost efficient approach to test unpopulated and populated board with open sockets, using a single probe. Specifically, a coaxial probe injects one frequency signal into the PWB trace, the phase shift between the reflected signal from the trace and the incident wave is detected and compared with the nominal value, which has been captured from a defect free board, which already underwent direct continuity and isolation testing. By applying this test solution to bed-of-nails equipment, we will be reducing 50 % of the probes, on the other by employing this solution to flying probes system with two probes, for a given design with NI isolated traces and NA adjacent pairs we will be reducing the number of tests from (NI+NA) tests to NI tests as isolation and continuity are performed in one go. Flying probes system involves mechanical movements, which dominate the test time, by reducing the number of the mechanical movements we will be increasing dramatically the test throughput. The conducted experiments have shown a good feasibility for practical use in the Automatic Test Equipment (ATE) for PWB and PCBA testing. At the highest sensitivity of the phase shift detector, the prototyped tester is capable to distinguish between a defective and error free board with significant margins in case of defects such as opens, DC and RF bridges, exceeded and different width lines. The margin in the measurement between a defective and a correct board, which depends on the type of the defect, is about 7 % to 68 %. In case of loaded board testing, the approach is capable in detecting opens with important margins, our test cases shown 40 % and 33 %, which makes it a strong candidate approach to be applied officially to PCBA testing where probing is feasible. The approach can be applied to the complete layout or to boost the test strategy where the applied test solutions are not covering 100 % of the possible defects.