Change search
Link to record
Permanent link

Direct link
BETA
Chouhan, Shailesh Singh
Alternative names
Publications (10 of 12) Show all publications
Chouhan, S. S. & Halonen, K. (2019). A 40 nW CMOS-Based Temperature Sensor with Calibration Free Inaccuracy within ±0.6 ◦C. Electronics, 8(11), Article ID 1275.
Open this publication in new window or tab >>A 40 nW CMOS-Based Temperature Sensor with Calibration Free Inaccuracy within ±0.6 ◦C
2019 (English)In: Electronics, ISSN 2079-9292, Vol. 8, no 11, article id 1275Article in journal (Refereed) Published
Abstract [en]

In this study, a temperature equivalent voltage signal was obtained by subtracting output voltages received from two individual temperature sensors. These sensors work in the subthreshold region and generate the output voltage signals that are proportional and complementary to the temperature. Over the temperature range of −40 ∘" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C to +85 ∘" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C without using any calibration method, absolute temperature inaccuracy less than ±0.6 ∘" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C was attained from the measurement of five prototypes of the proposed temperature sensor. The implementation was done in a standard 0.18 μ" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">μ m CMOS technology with a total area of 0.0018 mm 2" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">2. The total power consumption is 40 nW for a supply voltage of 1.2 V measured at room temperature.

Place, publisher, year, edition, pages
MDPI, 2019
Keywords
PTAT, CTAT, temperature sensor, CMOS, ultra low power, calibration free
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electronic systems
Identifiers
urn:nbn:se:ltu:diva-76593 (URN)10.3390/electronics8111275 (DOI)2-s2.0-85074401504 (Scopus ID)
Note

Validerad;2019;Nivå 2;2019-11-04 (svasva)

Available from: 2019-11-04 Created: 2019-11-04 Last updated: 2019-11-19Bibliographically approved
Sharma, V., Gopal, M., Singh, P., Vishvakarma1, S. K. & Chouhan, S. (2019). A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications. Analog Integrated Circuits and Signal Processing, 98(2), 331-346
Open this publication in new window or tab >>A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications
Show others...
2019 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 98, no 2, p. 331-346Article in journal (Refereed) Published
Abstract [en]

With the increased requirement of on-chip data computations in internet of things based applications, the embedded on-chip SRAM memory has been under its renovation stage to overcome the classical problems like stability and poor energy efficiency. In this work, a data-dependent-power-supply mechanism for a new 11T SRAM cell is proposed with ultra-low leakage and improved read/write stability against the process–voltage–temperature variations. The proposed cell consumes static power in the fraction of picowatt range and has considerable enhancement in the value of write static noise margin (WSNM). In addition, the use of associated read decoupling approach, with the column-based read buffer, further improves the read stability of the proposed cell and make it comparable with the hold stability value. The percentage reduction in the leakage power of proposed 11T cell is 99.97%">99.97% 99.97% , 99.93%">99.93% 99.93% and 99.97%">99.97% 99.97% , while the WSNM 1 is 6.98×">6.98× 6.98× , 3.12×">3.12× 3.12× and 1.46×">1.46× 1.46× , and WSNM 0 is 5.55×">5.55× 5.55× , 1.25×">1.25× 1.25× and 1.16×">1.16× 1.16× larger when operating at 0.4 V and compared to the conventional 6T and threshold voltage techniques based VTH_9T and data aware write assist (DAWA) 12T SRAM cell structures respectively. Iread/Ileak">I read /I leak  Iread/Ileak ratio for the proposed cell has improved by 6.55×">6.55× 6.55× , 6.22×">6.22× 6.22× and 5.11×">5.11× 5.11× when compared with the 6T, VTH_9T and DAWA12T SRAM to increase the memory density. Further, the post-layout Monte Carlo simulation results (2000 samples) confirm the robustness of the proposed cell against the process variations.

Place, publisher, year, edition, pages
Springer, 2019
Keywords
static random access memory (SRAM), Ultra-low power, Static noise margin (SNM), Write ability, Internet of things (IoT)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Industrial Electronics
Identifiers
urn:nbn:se:ltu:diva-70531 (URN)10.1007/s10470-018-1286-2 (DOI)000458231900010 ()2-s2.0-85052078005 (Scopus ID)
Note

Validerad;2019;Nivå 2;2019-03-08 (johcin)

Available from: 2018-08-22 Created: 2018-08-22 Last updated: 2019-03-08Bibliographically approved
Khan, S., Shah, A. P., Gupta, N., Chouhan, S. S., Pandey, J. G. & Vishvakarma, S. K. (2019). An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications. Microelectronics Journal, 92, Article ID 104605.
Open this publication in new window or tab >>An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications
Show others...
2019 (English)In: Microelectronics Journal, ISSN 0959-8324, Vol. 92, article id 104605Article in journal (Refereed) Published
Abstract [en]

Physically Unclonable Functions (PUF) have emerged as security primitives which can generate high entropy, temper resilient bits for security applications. However, the power budget of the ring oscillator (RO) PUF limits the use of RO PUF in IoT applications, in this concern a low power variant of RO PUF is much needed. In this paper, we have presented an ultra-low power, lightweight, configurable RO PUF based on the 4T XOR architecture. The proposed architecture is aging resilient; hence it produces a stable PUF output over the years. Also, it has a large number of challenge-response-pair (CRP) compared to the other architectures, which makes it suitable for chip identification as well as cryptographic key generation. The proposed PUF is implemented on 40 nm CMOS technology, and for the validation of design, we have also implemented on FPGA. The simulation results show that it has a uniqueness of 0.489 and worst-case reliability of 96.43% and 93.15% at 125 °C and 1.2 V, respectively. Compared to the conventional RO PUF it consumes 98.06% and 95.47% less dynamic and leakage power, respectively.

Place, publisher, year, edition, pages
Elsevier, 2019
Keywords
Lightweight, Low power architecture, Physically unclonable functions, Reliability, NBTI, IoT, Challenge-response pair, Security
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electronic systems
Identifiers
urn:nbn:se:ltu:diva-75630 (URN)10.1016/j.mejo.2019.104605 (DOI)000492862100009 ()
Note

Validerad;2019;Nivå 2;2019-11-22 (johcin)

Available from: 2019-08-21 Created: 2019-08-21 Last updated: 2019-11-22Bibliographically approved
Bhoi, B. K., Misa, N. K., Chouhan, S. S. & Acharya, S. (2019). Analyzing Design Parameters of Nano-Magnetic Technology Based Converter Circuit. In: Dr. Anirban Sengupta, Dr. Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma (Ed.), VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Revised Selected Papers. Paper presented at 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019 (pp. 34-46). Springer
Open this publication in new window or tab >>Analyzing Design Parameters of Nano-Magnetic Technology Based Converter Circuit
2019 (English)In: VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Revised Selected Papers / [ed] Dr. Anirban Sengupta, Dr. Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma, Springer, 2019, p. 34-46Conference paper, Published paper (Refereed)
Abstract [en]

Digital circuits need improvement in computation speed, reducing circuit complexity and power consumption. Emerging Technology NML can be such an architecture at nano-scale and thus emerges as a viable alternative for the digital CMOS VLSI. This technology has the capability to compute the logic as well as storage into the same device, which points out that it great potential for emerging technology. Since Nano-magnetic, technology fast approaches its minimal feature size, high device density and operate at room temperature. NML based circuits synthesis has to opt for novel half subtraction and Binary-to-Gray architecture for achieving minimal complexity and high-speed performance. This manuscript pro-poses area efficient binary half-subtraction and Binary-to-Gray converter architecture. Circuits’ synthesize are performed by MagCAD tool and simulate by Modelsim simulator. The circuit’s performance are estimated over other existing designs. The proposed converter consume 73.73%, and 94.49% less area than the converter designed using QCA and CMOS technique respectively. This is a significant contribution to this paper. Simulation results of converter show that the critical path delay falls within 0.15 µs.

Place, publisher, year, edition, pages
Springer, 2019
Keywords
Nano-magnetic logic, Binary-to-gray converter, Magnetic anisotropy, Minority voter, Perpendicular nano-magnetic logic
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electronic systems
Identifiers
urn:nbn:se:ltu:diva-75976 (URN)10.1007/978-981-32-9767-8_4 (DOI)978-981-329-766-1 (ISBN)
Conference
23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019
Available from: 2019-09-12 Created: 2019-09-12 Last updated: 2019-09-12Bibliographically approved
Al-Maqdasi, Z., Hajlane, A., Renbi, A., Ouarga, A., Chouhan, S. S. & Joffe, R. (2019). Conductive Regenerated Cellulose Fibers by Electroless Plating. Fibers, 7(5), Article ID 38.
Open this publication in new window or tab >>Conductive Regenerated Cellulose Fibers by Electroless Plating
Show others...
2019 (English)In: Fibers, ISSN 2079-6439, Vol. 7, no 5, article id 38Article in journal (Refereed) Published
Abstract [en]

Continuous metallized regenerated cellulose fibers for advanced applications (e.g. multi-functional composites) are produced by electroless copper plating. Copper is successfully deposited on the surface of cellulose fibers using commercial cyanide-free electroless copper plating package commonly available for manufacturing of printed wiring boards. The deposited copper is found to enhance the thermal stability, electrical conductivity and resistance to moisture uptake of the fibers. On the other hand, involved chemistry results in altering the molecular structure of the fibers as is indicated by the degradation of their mechanical performance (tensile strength and modulus).

Place, publisher, year, edition, pages
Basel: MDPI, 2019
Keywords
cellulose fibers, functionalization, copper coating, electroless plating, continuous fibers
National Category
Materials Engineering Other Electrical Engineering, Electronic Engineering, Information Engineering Composite Science and Engineering
Research subject
Polymeric Composite Materials; Industrial Electronics
Identifiers
urn:nbn:se:ltu:diva-73739 (URN)10.3390/fib7050038 (DOI)000470958000002 ()2-s2.0-85070398485 (Scopus ID)
Funder
The Swedish Foundation for International Cooperation in Research and Higher Education (STINT), IB2017-7389
Note

Validerad;2019;Nivå 2;2019-07-01 (johcin)

Available from: 2019-04-24 Created: 2019-04-24 Last updated: 2019-08-30Bibliographically approved
Khan, S., Gupta, N., Vishvakarma, A., Chouhan, S. S., Pandey, J. G. & Vishvakarma, S. K. (2019). Dual-Edge Triggered Lightweight Implementation of AES for IoT Security. In: Sengupta A., Dasgupta S., Singh V., Sharma R., Kumar Vishvakarma S. (Ed.), VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Revised Selected Papers. Paper presented at 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019 (pp. 298-307). Springer
Open this publication in new window or tab >>Dual-Edge Triggered Lightweight Implementation of AES for IoT Security
Show others...
2019 (English)In: VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Revised Selected Papers / [ed] Sengupta A., Dasgupta S., Singh V., Sharma R., Kumar Vishvakarma S., Springer, 2019, p. 298-307Conference paper, Published paper (Refereed)
Abstract [en]

Internet of Things (IoT) is now a growing part of our life. More than 10 billion devices are already connected, and more are expected to be deployed in the next coming years. To provide a practical solution for security, privacy and trust is the main concern for deploying IoT in such a large scale. For security and privacy in IoT, cryptography is the required solutions. AES algorithm is a well known, highly secure and symmetric key algorithm, but the area and power budget of AES makes it unsuitable for IoT Security. In this paper, we have presented a lightweight implementation of AES, with dual-edge triggered S-box. The proposed architecture has been implemented on FPGA as well as in ASIC on 180 nm technology. The proposed architecture uses a 32-bit data path to encrypt 128-bit plain-text with 128-bit cipher-key. ASIC implementation of the proposed architecture results in low-power (122.7 μ" role="presentation" style="box-sizing: border-box; display: inline-table; line-height: normal; letter-spacing: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; max-height: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">μμW at 1 V) consumption with a reduction in the hardware overhead by 30% and a throughput of 23 Mbps at 10 MHz clock frequency.

Place, publisher, year, edition, pages
Springer, 2019
Series
Communications in Computer and Information Science ; 1066
Keywords
Lightweight, Dual-edge triggered, AES Architecture, IoT, Security
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electronic systems
Identifiers
urn:nbn:se:ltu:diva-75978 (URN)10.1007/978-981-32-9767-8_26 (DOI)978-981-32-9766-1 (ISBN)
Conference
23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019
Available from: 2019-09-12 Created: 2019-09-12 Last updated: 2019-09-12Bibliographically approved
Sharma, V., Bisht, P., Dalal, A., Gopal, M., Vishvakarma, S. K. & Chouhan, S. S. (2019). Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications. AEU - International Journal of Electronics and Communications, 104(May), 10-22
Open this publication in new window or tab >>Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications
Show others...
2019 (English)In: AEU - International Journal of Electronics and Communications, ISSN 1434-8411, E-ISSN 1618-0399, Vol. 104, no May, p. 10-22Article in journal (Refereed) Published
Abstract [en]

This work presents a half-select free 12T SRAM cell with Data-Dependent Feedback Cutting approach to improve the write ability and isolated read path to enhance the read stability. The enhanced read and write ability is 1.95×" role="presentation"> and 2.84×" role="presentation"> larger respectively than that of the conventional 6T cell at 0.4 V. The half-select free behavior of proposed cell using the cross-point read/write structure facilitates the bit-interleaving memory architecture to effectively reduce the multi-bits soft error occurrence. The incorporated PMOS stacking effect in inverter pairs of the proposed cell offers the reduced leakage power which is 0.59×" role="presentation"> to that of 6T, at 0.4 V supply. To further minimize the leakage power at array level, the bit lines between two adjacent cells have been shared that consumes only 0.38×" role="presentation"> leakage power than that of the conventional 6T array for a 1 KB macro. Moreover, a Reconfigurable FPGA architecture is proposed for low power applications. The simulated static and active power consumption of 12T SRAM based reconfigurable FPGA is 0.22×" role="presentation"> and 0.45×" role="presentation"> when compared with the regular 12T FPGA. Finally, a Double Adjacent-bits Error Detection and Correction (DAEDC) scheme is suggested for the proposed bit-interleaved 12T SRAM array, to reduce the soft error effects.

Place, publisher, year, edition, pages
Elsevier, 2019
Keywords
Low power, Static random access memory (SRAM), Static noise margin (SNM), Leakage power, Error tolerance
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electronic systems
Identifiers
urn:nbn:se:ltu:diva-73997 (URN)10.1016/j.aeue.2019.02.018 (DOI)000467195000002 ()
Note

Validerad;2019;Nivå 2;2019-05-20 (oliekm)

Available from: 2019-05-20 Created: 2019-05-20 Last updated: 2019-06-18Bibliographically approved
Acharya, S., Chouhan, S. S. & Delsing, J. (2019). Scalability of Copper-Interconnects down to 3μm on Printed Boards by Laser-assisted-subtractive process. In: Proceedings of: 2019 IMAPS Nordic Conference on Microelectronics Packaging (NordPac): . Paper presented at 2019 IMAPS Nordic Conference on Microelectronics Packaging (NordPac), 11-13 June 2019, Copenhagen, Denmark (pp. 206-209). IEEE
Open this publication in new window or tab >>Scalability of Copper-Interconnects down to 3μm on Printed Boards by Laser-assisted-subtractive process
2019 (English)In: Proceedings of: 2019 IMAPS Nordic Conference on Microelectronics Packaging (NordPac), IEEE, 2019, p. 206-209Conference paper, Published paper (Refereed)
Abstract [en]

As per the latest roadmap of iNEMI, the global electronics market is emphasizing to identify disruptive technologies that can contribute towards denser, robust and tighter integration on the board level. Therefore, reduction in packaging factor of printed board can accommodate greater number of ICs to support miniaturization. This paper has shown an experimental method to pattern the metallic layer on a Printed circuit Board (PCB) to the smallest feature size. To investigate this, a commercially available FR-4 PCB with photosensitive material coat and a Copper (Cu) layer on it, is used. A reverse-mode Laser assisted writing is implemented to pattern the desired copper tracks. Soon after, a well-controlled development and chemical etching of the Laser-activated regions are done using Sodium Hydroxide solution followed by an aqueous solution of Sodium Persulfate. Current PCB interconnects used by the industries are of the order (~20 μm). Whereas the present work is a contribution towards achieving Copper interconnects with feature size 3.0μm. This miniaturization corresponds to 70% reduction in the feature size from 20 μm to 3μm. The natural adhesion of the Cu layer has remained intact even after the etching, shows the efficiency of the method adopted. Also, variation in the parameters such as etching time, etchant solution concentrations, temaperature, gain and exposure time of Laser beam and their corresponding effects are discussed. Other highlights of this subtractive method includes its cost-efficiency, lesser production time and repeatability.

Place, publisher, year, edition, pages
IEEE, 2019
Keywords
Subtractive process, FR-4 PCB, Laser assisted writing, etching, copper tracks, reverse-mode
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electronic systems
Identifiers
urn:nbn:se:ltu:diva-75980 (URN)10.23919/NORDPAC.2019.8760349 (DOI)
Conference
2019 IMAPS Nordic Conference on Microelectronics Packaging (NordPac), 11-13 June 2019, Copenhagen, Denmark
Available from: 2019-09-12 Created: 2019-09-12 Last updated: 2019-09-12Bibliographically approved
Sharma, V., Vishvakarma, S., Chouhan, S. S. & Halonen, K. (2018). A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes. International journal of circuit theory and applications, 46(12), 2314-2333
Open this publication in new window or tab >>A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes
2018 (English)In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 46, no 12, p. 2314-2333Article in journal (Refereed) Published
Abstract [en]

In this work, a data-dependent feedback-cutting–based bit-interleaved 12T static random access memory (SRAM) cell is proposed, which enhances the write margin in terms of write trip point (WTP) and write static noise margin (WSNM) by 2.14× and 8.99× whereas read stability in terms of dynamic read noise margin (DRNM) and read static noise margin (RSNM) by 1.06× and 2.6 ×, respectively, for 0.4 V when compared with a conventional 6T SRAM cell. The standby power has also been reduced to 0.93× with an area overhead of 1.49× as that of 6T. Monte Carlo simulation results show that the proposed cell offers a robust write margin when compared with the state-of-the-art memory cells available in the literature. An analytical model of WSNM for 12T operating in subthreshold region is also proposed, which has been verified using the simulation results. Finally, a small SRAM macro along with its independent memory controller has been designed. 

Place, publisher, year, edition, pages
John Wiley & Sons, 2018
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Industrial Electronics
Identifiers
urn:nbn:se:ltu:diva-70865 (URN)10.1002/cta.2555 (DOI)000452447300010 ()2-s2.0-85052789134 (Scopus ID)
Note

Validerad;2018;Nivå 2;2018-12-06 (svasva)

Available from: 2018-09-14 Created: 2018-09-14 Last updated: 2019-02-13Bibliographically approved
Yadav, D., Chouhan, S. S., Vishvakarma, S. & Raj, B. (2018). Application Specific Microcontroller Design for Internet of Things Based Wireless Sensor Network. Sensor Letters, 16(5), 374-385
Open this publication in new window or tab >>Application Specific Microcontroller Design for Internet of Things Based Wireless Sensor Network
2018 (English)In: Sensor Letters, ISSN 1546-198X, E-ISSN 1546-1971, Vol. 16, no 5, p. 374-385Article in journal (Refereed) Published
Abstract [en]

Today sensors are all over the place. We undervalue it, yet there are sensors in our vehicles, in our advanced cells, in processing plants controlling CO2 discharges, and even in the ground observing soil conditions in vineyards. WSN surprisingly cover the broad area of applications, and research and technology advance continuously increase their application field. The internet of things (IoT) introduced in correspondence to WSNs. WSN was traditionally recognized fundamental enabler for the IoT standard. WSNs make IoT applications valuable for both sensing and actuation. In this paper we design the microcontroller specifically for IoT based wireless sensor network. It takes the data from the different sensor node and send it to the gateway sensor node. We also design the Serial communication Peripheral (SPI) so that fast data transmission can be obtained very easily. Internal memory is used in the controller to hold the data for a short period, and then it is transmitted to the other wireless sensor node.

Place, publisher, year, edition, pages
American Scientific Publishers, 2018
Keywords
IOT, MICROCONTROLLER, RAM, ROM, SENSOR NODE, SERIAL COMMUNICATION INTERFACE (SPI), WIRELESS SENSOR NETWORK
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Industrial Electronics
Identifiers
urn:nbn:se:ltu:diva-70746 (URN)10.1166/sl.2018.3965 (DOI)
Note

Validerad;2018;Nivå 1;2018-12-04 (marisr)

Available from: 2018-09-04 Created: 2018-09-04 Last updated: 2018-12-04Bibliographically approved
Organisations

Search in DiVA

Show all publications