Ändra sökning
RefereraExporteraLänk till posten
Permanent länk

Direktlänk
Referera
Referensformat
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annat format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annat språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
Synthesis-Aided Reliability Assurance of Basic Block Models for Model Checking Purposes
Aalto University, Department of Electrical Engineering and Automation, Espoo, Finland; Computer Technology Department, ITMO University, St. Petersburg, Russian Federation.
VTT Technical Research Centre of Finland Ltd., Espoo, Finland.
Luleå tekniska universitet, Institutionen för system- och rymdteknik, Datavetenskap. Aalto University, Department of Electrical Engineering and Automation, Espoo, Finland.ORCID-id: 0000-0002-9315-9920
2018 (Engelska)Ingår i: Proceedings of the 2018 IEEE 27th International Symposium on Industrial Electronics (ISIE), IEEE, 2018, s. 669-674, artikel-id 8433793Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

In the Finnish nuclear industry, model checking, a formal verification technique, is used as an additional means of safety assurance for instrumentation and control (IC) system design. Since the code of vendor-specific basic function blocks used in IC is commonly closed, these blocks need to be modeled manually based on available specification. This modeling introduces an additional source of human factor into the verification process. To increase the reliability of the library of basic blocks used in nuclear IC verification, we apply formal synthesis techniques, which can construct finite-state models of reactive systems from behavior examples and temporal properties. Since these techniques have computational limitations and synthesized models are hard to understand even by an analyst, we do not use them in the final verification process. Instead, in an iterative process, behavioral differences between a synthesized model and a manual model implementation are identified and used to create a list of features of manual implementations which either violate the specification or show that the specification is ambiguous. 

Ort, förlag, år, upplaga, sidor
IEEE, 2018. s. 669-674, artikel-id 8433793
Nationell ämneskategori
Datavetenskap (datalogi)
Forskningsämne
Kommunikations- och beräkningssystem
Identifikatorer
URN: urn:nbn:se:ltu:diva-70797DOI: 10.1109/ISIE.2018.8433793Scopus ID: 2-s2.0-85052369562ISBN: 9781538637050 (tryckt)ISBN: 978-1-5386-3705-0 (digital)ISBN: 978-1-5386-3704-3 (tryckt)OAI: oai:DiVA.org:ltu-70797DiVA, id: diva2:1246437
Konferens
IEEE 27th International Symposium on Industrial Electronics, ISIE 2018; Cairns; Australia; 13-15 June 2018
Tillgänglig från: 2018-09-07 Skapad: 2018-09-07 Senast uppdaterad: 2018-09-07Bibliografiskt granskad

Open Access i DiVA

Fulltext saknas i DiVA

Övriga länkar

Förlagets fulltextScopus

Personposter BETA

Vyatkin, Valeriy

Sök vidare i DiVA

Av författaren/redaktören
Vyatkin, Valeriy
Av organisationen
Datavetenskap
Datavetenskap (datalogi)

Sök vidare utanför DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetricpoäng

doi
isbn
urn-nbn
Totalt: 3 träffar
RefereraExporteraLänk till posten
Permanent länk

Direktlänk
Referera
Referensformat
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annat format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annat språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf