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Closed-loop formal verification framework with non-determinism, configurable by meta-modelling
University of Auckland.ORCID iD: 0000-0003-2936-4185
2011 (English)In: Proceedings of the 37th IEEE Industrial Electronics Society (IECON 2011), Melbourne, VIC: IEEE Communications Society, 2011, p. 3770-3775Conference paper, Published paper (Refereed)
Abstract [en]

Formal verification of embedded control systems using closed-loop plant-controller models is getting increasingly popular. In this paper we propose a new method reducing complexity of model-checking on account of infusing non-determinism into certain parts of the plant model during formal verification process guided by a software tool. Net Condition/Event Systems (NCES) formalism is used for modular design of closed-loop models which are verified by ViVe and SESA model-checkers. Its performance is compared to modelling with finite state verified with SMV and UPPAAL and is proven to be superior.

Place, publisher, year, edition, pages
Melbourne, VIC: IEEE Communications Society, 2011. p. 3770-3775
National Category
Computer Sciences
Research subject
Dependable Communication and Computation Systems
Identifiers
URN: urn:nbn:se:ltu:diva-30946DOI: 10.1109/IECON.2011.6119923Local ID: 4f6dacaa-4325-40ba-8272-904339436243ISBN: 978-1-61284-969-0 (print)OAI: oai:DiVA.org:ltu-30946DiVA, id: diva2:1004175
Conference
Annual Conference of the IEEE Industrial Electronics Society : 07/11/2011 - 10/11/2011
Available from: 2016-09-30 Created: 2016-09-30 Last updated: 2018-04-03Bibliographically approved

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Patil, SandeepVyatkin, Valeriy
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CiteExportLink to record
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Citation style
  • apa
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  • de-DE
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  • Other locale
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Output format
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  • asciidoc
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