In a search of an appropriate visual specification language to be applied in control engineering the timing diagram specification language is suggested. It is applied to the verification of distributed controllers following the standard IEC 61499. Specification of inputs and outputs of the controller are given in the graphical form of signal diagrams. The inputs are then converted into finite-state models, while the diagram of outputs is used to build equivalent analytic expressions in extended CTL. These two parts are used in formal verification of the control system.