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Formal Verification of IEC61499 Function Blocks with Abstract State Machines and SMV -- Modelling
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Computer Science.ORCID iD: 0000-0003-2936-4185
University of Auckland, Penza State University, Department of Computer Science, University of Penza, Computer Science Department, Penza State University, Penza.
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Computer Science.ORCID iD: 0000-0002-9315-9920
Number of Authors: 32015 (English)In: IEEE TrustCom-BigDataSE-ISPA 2015: Helsinki, 20-22 Aug. 2015, Piscataway, NJ: IEEE Communications Society, 2015, Vol. 3, p. 313-320, article id 7345666Conference paper, Published paper (Refereed)
Abstract [en]

IEC 61499 Standard for Function Blocks Architecture is an executable component model for distributed embedded control system design that combines block diagrams and state machines. This paper proposes rules for formal modelling of IEC61499 function blocks for popular model checking environment of SMV using Abstract State Machines as an intermediate model. This paper first proposes a formal description of the IEC 61499 in abstract state machines (ASM). The formal description for main artifact of the standard (function block) is presented in the paper. The ASM model is further translated to the input format of the SMV model checker which is used to formally verify properties of applications developed in IEC 61499 standard. In this way the proposed verification framework enables the formal verification of the IEC 61499 control systems. The paper also highlights the other uses of verification such as portability of IEC 61499 based control applications across different implementation platforms compliant with the IEC 61499 standard. The formal model is applied on an example IEC 61499 controller, and the SMV model for the Basic Function block is explained in detail.

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE Communications Society, 2015. Vol. 3, p. 313-320, article id 7345666
National Category
Computer Sciences
Research subject
Dependable Communication and Computation Systems
Identifiers
URN: urn:nbn:se:ltu:diva-32663DOI: 10.1109/Trustcom.2015.650ISI: 000380431400045Scopus ID: 84969132840Local ID: 73823e11-9167-417d-a059-923ab1f4f53cISBN: 9781467379519 (print)OAI: oai:DiVA.org:ltu-32663DiVA, id: diva2:1005897
Conference
IEEE TrustCom-BigDataSE-ISPA : 20/08/2015 - 22/08/2015
Note

Validerad; 2016; Nivå 1; 2016-10-10 (andbra)

Available from: 2016-09-30 Created: 2016-09-30 Last updated: 2018-07-10Bibliographically approved
In thesis
1. Enhanced engineering of component-based industrial automation systems using formal methods
Open this publication in new window or tab >>Enhanced engineering of component-based industrial automation systems using formal methods
2018 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Industrial automation is facing challenges related to a manufacturing change from mass pro-duction to mass customization. As a result, the focus of automation has been shifting to flexi-bility, reconfigurability and safety assurance resulting in a new class of systems that is heavilymodular. We call this new class of systems as Component-Based industrial Automation Sys-tems (CBAS).

Given the current challenges and shift in focus, the current engineering practices and meth-ods need to be changed or upgraded. One of these practices is software verification and valida-tion (V&V) techniques. Simulation is one of the well-known V&V techniques used currentlyin CBAS. Simulation is performed by building simulation models for the physical process,for example, simulation using Matlab. However, development of simulation models is time-consuming and does not guarantee 100% validation of the automation control software makingjust simulation inadequate for CBAS. To address this problem, formal verification has beenconsidered as a proper complementary V&V technique. Discrete state model checking is oneof such approaches, which is the process of automatically verifying whether a set of desiredformal specifications is satisfied over the target system model. While model checking is com-putationally resource hungry, it has been successfully used in other adjacent areas of computersystems engineering, such as hardware design, proving its ability to handle problems of rea-sonably large complexity. This suggests that model checking can be applied in the industrialautomation domain, and there has been an impressive number of works towards this goal.

Despite moderate successes and promises the reality is that formal techniques are rarelyused in the development practice by industrial automation engineers. It seems that the existingtools and methods do not fit into the current Software Development Life Cycle (SDLC) of au-tomation systems engineering. This thesis first looks at current state of art with comprehensiveliterature review, identifying 3 main challenges for lack of industrial adoption of formal verifi-cation. The thesis then presents various formal method approaches to address these challenges.The main contribution of the thesis is a method for the formal verification of IEC 61499 func-tion block applications using Abstract State Machines (ASM) and model checking. A formaldescription for main artifacts of the standard is presented in the thesis. Further, ASM rules fortranslation for function blocks to the input format of the SMV model checker is presented. Inthis way, the proposed verification method enables the formal verification of the IEC 61499control systems.

As results, the thesis presents an application of this framework to industrial automation usecases to check for functional and non-functional requirements. It also presents use cases wherethe proposed framework is used for verifying portability of IEC 61499 based control applica-tions across different implementation platforms compliant with the IEC 61499 standard.

Place, publisher, year, edition, pages
Luleå: Luleå tekniska universitet, 2018. p. 300
Series
Doctoral thesis / Luleå University of Technology 1 jan 1997 → …, ISSN 1402-1544
National Category
Computer Systems Computer Sciences
Research subject
Dependable Communication and Computation Systems
Identifiers
urn:nbn:se:ltu:diva-68113 (URN)978-91-7790-082-5 (ISBN)978-91-7790-083-2 (ISBN)
Public defence
2018-05-29, A109, Luleå Campus, Luleå, 12:00 (English)
Opponent
Supervisors
Available from: 2018-04-03 Created: 2018-03-30 Last updated: 2018-05-17Bibliographically approved

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Patil, SandeepVyatkin, Valeriy

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