Change search
ReferencesLink to record
Permanent link

Direct link
Power and energy efficiency evaluation for HW and SW implementation of nxn matrix multiplication on Altera FPGAs
Jönköping University.
2009 (English)In: Proceedings of the 6th FPGA world Conference, FPGAworld '09, Association for Computing Machinery (ACM), 2009, 1-7 p.Conference paper (Refereed)
Abstract [en]

Matrix multiplication is most often involved in graphics, image processing, digital signal processing, robotics and control engineering applications. In this paper we compared and analyzed the power and energy consumption in three different designs, which multiply two matrices A and B of nxn 32-bit items and store the result in C matrix of nxn 64-bit items. The first two designs use FPGA HW with different number of storage registers 2n and 2n2 and the third design uses a computer system piloted by NIOS II\e processor with On-Chip memory. We showed that NIOS II\e is not an energy efficient alternative to multiply nxn matrices compared to HW matrix multiplier on FPGA.Since our target FPGA is the Altera cyclone II family, we also had to find one acceptable method to measure the real power consumption in the FPGA device.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2009. 1-7 p.
Research subject
Industrial Electronics
URN: urn:nbn:se:ltu:diva-37060DOI: 10.1145/1667520.1667526Local ID: aefcbc00-07c7-11e0-b767-000ea68e967bISBN: 978-1-60558-879-7 (print)OAI: diva2:1010558
FPGA World Conference : 10/09/2009 - 10/09/2009
Upprättat; 2009; 20101214 (abdren)Available from: 2016-10-03 Created: 2016-10-03

Open Access in DiVA

No full text

Other links

Publisher's full text

Search in DiVA

By author/editor
Renbi, Abdelghani

Search outside of DiVA

GoogleGoogle Scholar

Altmetric score

Total: 17 hits
ReferencesLink to record
Permanent link

Direct link