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Design and implementation of a DDR SDRAM controller for system on chip
2003 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

The aim of this study was to investigate the different problems associated with the design and implementation of a DDR SDRAM Controller for CMOS technology. This study has lead to a working implementation of a DDR SDRAM Controller that is meant to be used as a reference for future implementations. The report highlight design issues and propose solutions to problems like data resynchronization and how to phase shift the data strobe. The result of this study highlights design issues common to any Double Data Rate interface that can be used when designing and implementing applications in need of the higher performance given by a Double Data Rate interface and is not limited to the design and implementation of a DDR SDRAM Controller.

Place, publisher, year, edition, pages
2003.
Keyword [en]
Technology, DDR, SDRAM, Interface, Memory Controller, CMOS
Keyword [sv]
Teknik
Identifiers
URN: urn:nbn:se:ltu:diva-47021ISRN: LTU-EX--03/038--SELocal ID: 49d1340e-33e3-423f-bc4d-eb975566a9e9OAI: oai:DiVA.org:ltu-47021DiVA: diva2:1020337
Subject / course
Student thesis, at least 30 credits
Educational program
Computer Science and Engineering, master's level
Examiners
Note
Validerat; 20101217 (root)Available from: 2016-10-04 Created: 2016-10-04Bibliographically approved

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