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Comparison and selection of an electronic architecture for a new type of motor breaker drive
2004 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

In this masters thesis a new electronic architecture for control of a new type of medium voltage motor breaker drive is selected and evaluated. The new type of circuit breaker has an operating mechanism that uses algorithms that predict the zero current crossings in each phase and is able to perform an arc free interruption. A functional prototype exists that shows that the new type of medium voltage breaker system synchronized to line current and voltage is possible. The existing prototype is not ready to be manufactured due to use of exotic and high cost components in combination with a layout that does not fit a standard size printed circuit board. The main goal of the thesis work is to find a more cost effective architecture and with reduced PCB layout size. Important topics for the project are single versus multiprocessor architecture and selection of a processor to implement the main control algorithms. The goal of a cost effective architecture is achieved by re-use of circuitry from an exciting motor breaker drive in combination with the use of a new motor control DSP. A higher inter-process communication bandwidth combined with more computational demanding algorithms are reasons why an existing four DSP architecture can’t be used in this application. A new dual DSP architecture with detailed design of functionality and choice of components is presented together with an estimation of cost. Test results are also presented that shows that the new DSP is able to handle and perform the required calculations in a dual DSP architecture. Test results shows that each DSP is loaded to less then 50% during “worst case” execution of existing software. A serial bus is evaluated and decided to be used for inter processor communication. The serial bus used is proven to have the required bandwidth for this application and makes the communication between the two DSPs simple and cost effective. Finally a cost estimation shows that a dual DSP architecture can be made cost effective compared to the existing functional prototype with a component cost of less then 120 USD.

Place, publisher, year, edition, pages
Keyword [en]
Technology, Digital signal processor, arc free operation, medium voltage, breaker, PWM, Converter, A/D-converter
Keyword [sv]
URN: urn:nbn:se:ltu:diva-50903ISRN: LTU-EX--04/135--SELocal ID: 81c012de-621c-4158-98eb-232c2756f4bcOAI: diva2:1024266
Subject / course
Student thesis, at least 30 credits
Educational program
Electrical Engineering, master's level
Validerat; 20101217 (root)Available from: 2016-10-04 Created: 2016-10-04Bibliographically approved

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