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eStage - an FPGA based real-time jamming solution
2003 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Today the infrastructure of computer networks is well developed, with a constant increase of speed and capacity, which makes it possible to use them in new ways. One possible application is to let musicians play together in real-time over the Internet even if many miles separate them, which is the subject of this thesis. Musicians are a fastidious people: they will not accept long delays in the sound between them when they are playing together. A test with professional musicians was conducted to determine the maximum acceptable delay. The test results showed that a delay in the range of 20ms between the participating musicians was acceptable. To achieve such short delays a strict control of the platform is important. A software solution on a standard PC is simply not feasible since the operating system and its device drivers make it very hard to control the complete dataflow. This report describes the work of implementing a real-time music system based on a Field Programmable Gate Array (FPGA). The result of the work is a fully functional prototype with total control over the dataflow, which ensures a very low internal delay.

Place, publisher, year, edition, pages
Keyword [en]
Technology, FPGA, PIC, VHDL, Jamming, RealTime
Keyword [sv]
URN: urn:nbn:se:ltu:diva-55643ISRN: LTU-EX--03/126--SELocal ID: c7bdb667-4176-4fe6-9089-7372eb2c1c60OAI: diva2:1029027
Subject / course
Student thesis, at least 30 credits
Educational program
Computer Science and Engineering, master's level
Validerat; 20101217 (root)Available from: 2016-10-04 Created: 2016-10-04Bibliographically approved

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