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Network Processor SoC Architecture
2002 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

The massive expansion of the Internet stresses the need for a highly scalable infrastructure that allows expansion in a pace required by society. Today, dedicated hardware, ASICs, is responsible for handling the majority of the Internet traffic. The problem with ASICs is that they are inflexible and cannot easily be adapted to new requirements. A possible solution to meet the needs of tomorrow is the network processor. A fundamental description of a network processor is that software is used to control how the traffic should be handled, thus new functionality can be added by developing new software. An objective for our work was to develop a model of a network processor capable of processing traffic from one Gigabit and eight Fast Ethernet connections. A number of different architectural issues were examined in order to design a new network processor. The design was implemented in a hardware description language in order to make it feasible to verify functionality and performance. To ensure that it was a viable solution, the design was taken through an ASIC design flow with the aid of modern EDA tools. The result is a highly scalable architecture of a network processor suitable for e.g. a corporate or university backbone. The main finding of this thesis is that, even though the network processor paradigm is likely to have its niche in the networking society, the problem of meeting both technical and economical requirements at the same time implies that it is unlikely that the concept is a panacea for all network problems.

Place, publisher, year, edition, pages
2002.
Keyword [en]
Technology, network processors architecture
Keyword [sv]
Teknik
Identifiers
URN: urn:nbn:se:ltu:diva-57176ISRN: LTU-EX--02/197--SELocal ID: ddd08e6a-a34e-4d3e-817e-f64bf2110f3dOAI: oai:DiVA.org:ltu-57176DiVA, id: diva2:1030563
Subject / course
Student thesis, at least 30 credits
Educational program
Computer Science and Engineering, master's level
Examiners
Note
Validerat; 20101217 (root)Available from: 2016-10-04 Created: 2016-10-04Bibliographically approved

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CiteExportLink to record
Permanent link

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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf