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A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications
Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore .
Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore .
Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore .
Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore .
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2019 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 98, no 2, p. 331-346Article in journal (Refereed) Published
Abstract [en]

With the increased requirement of on-chip data computations in internet of things based applications, the embedded on-chip SRAM memory has been under its renovation stage to overcome the classical problems like stability and poor energy efficiency. In this work, a data-dependent-power-supply mechanism for a new 11T SRAM cell is proposed with ultra-low leakage and improved read/write stability against the process–voltage–temperature variations. The proposed cell consumes static power in the fraction of picowatt range and has considerable enhancement in the value of write static noise margin (WSNM). In addition, the use of associated read decoupling approach, with the column-based read buffer, further improves the read stability of the proposed cell and make it comparable with the hold stability value. The percentage reduction in the leakage power of proposed 11T cell is 99.97%">99.97% 99.97% , 99.93%">99.93% 99.93% and 99.97%">99.97% 99.97% , while the WSNM 1 is 6.98×">6.98× 6.98× , 3.12×">3.12× 3.12× and 1.46×">1.46× 1.46× , and WSNM 0 is 5.55×">5.55× 5.55× , 1.25×">1.25× 1.25× and 1.16×">1.16× 1.16× larger when operating at 0.4 V and compared to the conventional 6T and threshold voltage techniques based VTH_9T and data aware write assist (DAWA) 12T SRAM cell structures respectively. Iread/Ileak">I read /I leak  Iread/Ileak ratio for the proposed cell has improved by 6.55×">6.55× 6.55× , 6.22×">6.22× 6.22× and 5.11×">5.11× 5.11× when compared with the 6T, VTH_9T and DAWA12T SRAM to increase the memory density. Further, the post-layout Monte Carlo simulation results (2000 samples) confirm the robustness of the proposed cell against the process variations.

Place, publisher, year, edition, pages
Springer, 2019. Vol. 98, no 2, p. 331-346
Keywords [en]
static random access memory (SRAM), Ultra-low power, Static noise margin (SNM), Write ability, Internet of things (IoT)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Industrial Electronics
Identifiers
URN: urn:nbn:se:ltu:diva-70531DOI: 10.1007/s10470-018-1286-2ISI: 000458231900010Scopus ID: 2-s2.0-85052078005OAI: oai:DiVA.org:ltu-70531DiVA, id: diva2:1240635
Note

Validerad;2019;Nivå 2;2019-03-08 (johcin)

Available from: 2018-08-22 Created: 2018-08-22 Last updated: 2019-03-08Bibliographically approved

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Chouhan, Shailesh

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