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Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications
Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, India.
Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, India.
Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, India.
Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, India.
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2019 (English)In: AEU - International Journal of Electronics and Communications, ISSN 1434-8411, E-ISSN 1618-0399, Vol. 104, no May, p. 10-22Article in journal (Refereed) Published
Abstract [en]

This work presents a half-select free 12T SRAM cell with Data-Dependent Feedback Cutting approach to improve the write ability and isolated read path to enhance the read stability. The enhanced read and write ability is 1.95×" role="presentation"> and 2.84×" role="presentation"> larger respectively than that of the conventional 6T cell at 0.4 V. The half-select free behavior of proposed cell using the cross-point read/write structure facilitates the bit-interleaving memory architecture to effectively reduce the multi-bits soft error occurrence. The incorporated PMOS stacking effect in inverter pairs of the proposed cell offers the reduced leakage power which is 0.59×" role="presentation"> to that of 6T, at 0.4 V supply. To further minimize the leakage power at array level, the bit lines between two adjacent cells have been shared that consumes only 0.38×" role="presentation"> leakage power than that of the conventional 6T array for a 1 KB macro. Moreover, a Reconfigurable FPGA architecture is proposed for low power applications. The simulated static and active power consumption of 12T SRAM based reconfigurable FPGA is 0.22×" role="presentation"> and 0.45×" role="presentation"> when compared with the regular 12T FPGA. Finally, a Double Adjacent-bits Error Detection and Correction (DAEDC) scheme is suggested for the proposed bit-interleaved 12T SRAM array, to reduce the soft error effects.

Place, publisher, year, edition, pages
Elsevier, 2019. Vol. 104, no May, p. 10-22
Keywords [en]
Low power, Static random access memory (SRAM), Static noise margin (SNM), Leakage power, Error tolerance
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electronic systems
Identifiers
URN: urn:nbn:se:ltu:diva-73997DOI: 10.1016/j.aeue.2019.02.018ISI: 000467195000002OAI: oai:DiVA.org:ltu-73997DiVA, id: diva2:1316707
Note

Validerad;2019;Nivå 2;2019-05-20 (oliekm)

Available from: 2019-05-20 Created: 2019-05-20 Last updated: 2019-06-18Bibliographically approved

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Chouhan, Shailesh Singh

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