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Dual-Edge Triggered Lightweight Implementation of AES for IoT Security
Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, India.
Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, India.
Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, India.
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
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2019 (English)In: VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Revised Selected Papers / [ed] Sengupta A., Dasgupta S., Singh V., Sharma R., Kumar Vishvakarma S., Springer, 2019, p. 298-307Conference paper, Published paper (Refereed)
Abstract [en]

Internet of Things (IoT) is now a growing part of our life. More than 10 billion devices are already connected, and more are expected to be deployed in the next coming years. To provide a practical solution for security, privacy and trust is the main concern for deploying IoT in such a large scale. For security and privacy in IoT, cryptography is the required solutions. AES algorithm is a well known, highly secure and symmetric key algorithm, but the area and power budget of AES makes it unsuitable for IoT Security. In this paper, we have presented a lightweight implementation of AES, with dual-edge triggered S-box. The proposed architecture has been implemented on FPGA as well as in ASIC on 180 nm technology. The proposed architecture uses a 32-bit data path to encrypt 128-bit plain-text with 128-bit cipher-key. ASIC implementation of the proposed architecture results in low-power (122.7 μ" role="presentation" style="box-sizing: border-box; display: inline-table; line-height: normal; letter-spacing: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; max-height: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">μμW at 1 V) consumption with a reduction in the hardware overhead by 30% and a throughput of 23 Mbps at 10 MHz clock frequency.

Place, publisher, year, edition, pages
Springer, 2019. p. 298-307
Series
Communications in Computer and Information Science ; 1066
Keywords [en]
Lightweight, Dual-edge triggered, AES Architecture, IoT, Security
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electronic systems
Identifiers
URN: urn:nbn:se:ltu:diva-75978DOI: 10.1007/978-981-32-9767-8_26ISBN: 978-981-32-9766-1 (print)OAI: oai:DiVA.org:ltu-75978DiVA, id: diva2:1350935
Conference
23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019
Available from: 2019-09-12 Created: 2019-09-12 Last updated: 2019-09-12Bibliographically approved

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Chouhan, Shailesh Singh

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