Internet of Things (IoT) is now a growing part of our life. More than 10 billion devices are already connected, and more are expected to be deployed in the next coming years. To provide a practical solution for security, privacy and trust is the main concern for deploying IoT in such a large scale. For security and privacy in IoT, cryptography is the required solutions. AES algorithm is a well known, highly secure and symmetric key algorithm, but the area and power budget of AES makes it unsuitable for IoT Security. In this paper, we have presented a lightweight implementation of AES, with dual-edge triggered S-box. The proposed architecture has been implemented on FPGA as well as in ASIC on 180 nm technology. The proposed architecture uses a 32-bit data path to encrypt 128-bit plain-text with 128-bit cipher-key. ASIC implementation of the proposed architecture results in low-power (122.7 μ" role="presentation" style="box-sizing: border-box; display: inline-table; line-height: normal; letter-spacing: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; max-height: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">μμW at 1 V) consumption with a reduction in the hardware overhead by 30% and a throughput of 23 Mbps at 10 MHz clock frequency.