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Scalability of Copper-Interconnects down to 3μm on Printed Boards by Laser-assisted-subtractive process
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.ORCID iD: 0000-0001-8774-9433
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.ORCID iD: 0000-0002-6055-3198
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.ORCID iD: 0000-0002-4133-3317
2019 (English)In: Proceedings of: 2019 IMAPS Nordic Conference on Microelectronics Packaging (NordPac), IEEE, 2019, p. 17-20Conference paper, Published paper (Refereed)
Abstract [en]

As per the latest roadmap of iNEMI, the global electronics market is emphasizing to identify disruptive technologies that can contribute towards denser, robust and tighter integration on the board level. Therefore, reduction in packaging factor of printed board can accommodate greater number of ICs to support miniaturization. This paper has shown an experimental method to pattern the metallic layer on a Printed circuit Board (PCB) to the smallest feature size. To investigate this, a commercially available FR-4 PCB with photosensitive material coat and a Copper (Cu) layer on it, is used. A reverse-mode Laser assisted writing is implemented to pattern the desired copper tracks. Soon after, a well-controlled development and chemical etching of the Laser-activated regions are done using Sodium Hydroxide solution followed by an aqueous solution of Sodium Persulfate. Current PCB interconnects used by the industries are of the order (~20 μm). Whereas the present work is a contribution towards achieving Copper interconnects with feature size 3.0μm. This miniaturization corresponds to 70% reduction in the feature size from 20 μm to 3μm. The natural adhesion of the Cu layer has remained intact even after the etching, shows the efficiency of the method adopted. Also, variation in the parameters such as etching time, etchant solution concentrations, temaperature, gain and exposure time of Laser beam and their corresponding effects are discussed. Other highlights of this subtractive method includes its cost-efficiency, lesser production time and repeatability.

Place, publisher, year, edition, pages
IEEE, 2019. p. 17-20
Keywords [en]
Subtractive process, FR-4 PCB, Laser assisted writing, etching, copper tracks, reverse-mode
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electronic Systems
Identifiers
URN: urn:nbn:se:ltu:diva-75980DOI: 10.23919/NORDPAC.2019.8760349Scopus ID: 2-s2.0-85073892655OAI: oai:DiVA.org:ltu-75980DiVA, id: diva2:1350938
Conference
2019 IMAPS Nordic Conference on Microelectronics Packaging (NordPac), 11-13 June 2019, Lyngby, Denmark
Note

Funder: European Project: Productive 4.0;

ISBN for host publication: 978-1-7281-2884-9, 978-91-519-2090-0

Available from: 2019-09-12 Created: 2019-09-12 Last updated: 2024-05-21Bibliographically approved
In thesis
1. An SBU fully additive production approach for Board-level Electronics Packaging (SBU-CBM Method)
Open this publication in new window or tab >>An SBU fully additive production approach for Board-level Electronics Packaging (SBU-CBM Method)
2021 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

The worldwide electronics market is focusing on developing innovative technologies that can lead to denser, more resilient, and tighter board-level integration. The consumer electronics market is trending toward miniaturization, with HDI-PCBs dominating. Electronics shrinking and scaling technology is the prime concern of all manufacturers. The PCBA industry is transforming its production practices which can reduce the solder joints, limit the usage of discrete and bulky components, reduce the packaging factor of printed boards by accommodating the maximum number of ICs, minimize the assembly span, optimize the latency, and so on. However, developments in production processes in the PCB manufacturing industry need more attention than those in  Silicon-based (ICs) fabrications. One of the issues in PCB fabrication is utilizing conventional metallization approaches. The majority of manufacturers continue to use standard Copper(Cu) laminates on the base substrate and lithography methods to shape the structures.In recent manufacturing technologies, semi-Additive process (SAP) or modified-SAP (mSAP) methods are being adopted to replace traditional subtractive print-and-etch procedures. To scale down the Lines and Spaces (L\&S) on PCBs comparable to that of IC-level, most smartphone makers use Substrate-like PCB (SLP) using mSAP methods. However, subtractive patterning has been used in the intermediate stages of fabrication in those methods. This thesis demonstrates a fully additive selective metallization-based production approach to bridge this technology gap between IC-level and board-level fabrications. The fabrication process has given the name 'Sequential Build-Up Covalent Bonded Metallisation' (SBU-CBM) method.

This dissertation presents a new approach to Cu metallization using a significant step reducing-pattern-transfer process. The patterning method activates a seed layer of CBM polymer chains on a polymer surface with optimal UV-Laser settings. This surface modification enables a strong Copper (Cu) bonding onto the modified surface by Cu-plating. The suggested approach generated a 2.5D surface pattern using a micrometer via laser ablation and subsequent sub-micrometer laser lithography. Furthermore, the surface characterization of each step involved in the fabrication process is analysed and presented to show the sequential growth of layers on top of each other. To investigate the mechanism of the process at the interfaces, characterizations such as EDS, SEM, and XRD characterizations were performed. This PCB manufacturing method can selectively add metallic layers to the finest feature sizes at considerably lower temperatures. Overall, the thesis has addressed two critical aspects i.e. miniaturization of interconnects at board-level and the feasibility of a fully-additive production approach for electronics packaging.

First, a subtractive method is shown to achieve Copper interconnects with feature size 3.0$\mu$m. This miniaturization corresponds to 70\% reduction in the feature size from 20 $\mu$m to 3 $\mu$m. Next, the proposed additive production process has produced Cu interconnects with feature sizes of 2.5 $\mu$m L\&S and via of diameter 10 $\mu$m. The scaling of the interconnects was achieved by optimizing the process parameters involved in the proposed fabrication recipe.

Second, the sequential build-up (SBU) procedure is adopted to realize the embedded passives with the minimum possible feature size ($<$ 10 $\mu$m). An embedded capacitor and a planar inductor were fabricated. The proposed method can be employed to achieve any desirable pattern on FR-4, and a few of them are shown in the thesis. This additive technique can further be investigated through electrical and reliability assessment to make it an industrially accepted method.

Place, publisher, year, edition, pages
Luleå University of Technology, 2021
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Cyber-Physical Systems
Identifiers
urn:nbn:se:ltu:diva-88609 (URN)978-91-8048-001-7 (ISBN)978-91-8048-002-4 (ISBN)
Presentation
2022-02-25, E632, 10:00 (English)
Supervisors
Available from: 2021-12-30 Created: 2021-12-29 Last updated: 2022-02-10Bibliographically approved

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Acharya, SarthakChouhan, Shailesh SinghDelsing, Jerker

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