The motivation of the thesis is to develop a System on Chip (SoC) design with the softcore RISC-V toprovide the EtherCAT(Ethernet for Control Automation Technology) slave communication for CAESARspace robot whose backbone communication system bus is provided by EtherCAT protocol. CAESARis a space mission project of Institute of Robotics andMechatronics at DLR and the current concept ofCAESAR’s Joint Control Units (JCU) are desired to improve due to design complexity of the JCU’s electronicunits. In this thesis, the design complexity is reduced with the operation of EtherCAT slave communicationthrough FPGA-based RISC-V IP core instead of using several Digital Signal Processors (DSPs) to utilize fornew concept of the electronic units.The work was performed by following four parts. The first one established a design of RISC-V subsystemwhich provides the configuration of the soft core RISC-V and interconnection with the other moduleson the FPGA design. As a second part, a bridge was designed in VHDL hardware description languageto operate as AXI slave for efficient data transfers and Process Data Interface (PDI) to access the Ether-CAT slave. With the integration of the subsystem and the bridge, the SoC design was performed. In thethird part, the SoC design was tested by the software implementation into the application layer of Ether-CAT slave. Finally, the EtherCAT communication through the SoC designwas validated by EtherCAT master.After the successful tests and the validation, the work shows that the SoC design can be conveniently usedfor the communication system of CAESAR’s Joint Control Units (JCU) by avoiding a complex design.