Physically unclonable functions (PUF) emerged as security primitives that generate high entropy, temper resilient bits for security applications. However, the implementation area budget limits their use in lightweight applications such as IoT, RFID, and biomedical applications. In the form of SRAM or D flip-flop, intrinsic PUFs are abundantly available in almost all of the designs. Being an integral part of the design, they can be used with compromised performance. In this work, to address the usage of intrinsic PUF, a D flip-flop based lightweight PUF is proposed. The proposed architecture is implemented on 40 nm CMOS technology. The simulation results show that it offers a uniqueness of 0.502 and the worst-case reliability of 95.89% at high temperature 125 °C and 97.89% at a supply voltage of 1.2 V. To evaluate the performance of various PUF architectures, A novel term, the uniqueness-to-reliability ratio, is proposed. When compared to the conventional D flip-flop, it offers 4.491 times more uniqueness and 127.74 times more uniqueness-to-reliability ratio with the same layout area. Since it uses the symmetrical structure, unlike other architectures, the proposed architecture does not require any post-processing schemes for bias removal, which further saves the silicon area. To verify the functional correctness of the simulation results, an FPGA implementation of the conventional and proposed D Flip-flop is also presented.