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Realization of Embedded Passives using an additive Covalent bonded metallization approach
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.ORCID iD: 0000-0001-8774-9433
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.ORCID iD: 0000-0002-6055-3198
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.ORCID iD: 0000-0002-4133-3317
2019 (English)In: 2019 22nd European Microelectronics and Packaging Conference & Exhibition (EMPC): Technical Papers, IEEE, 2019Conference paper, Published paper (Other academic)
Abstract [en]

Miniaturization is the call of the day. Electronics shrinking and scaling technology is the priority of all manufacturers. PCBA Industry is working towards the elimination of solder joints, reduction in use of discrete and bulky components, lowering of assemble span, minimized latency etc. Embedded passive technology is playing a significant role in this roadmap by providing better signal performance, reduced parasitic and crosstalk. In this work, the primary focus is to develop a cost-efficient and flexible fabrication methodology that will be suitable for bulk production. A sequential build up (SBU) procedure is adopted with an additive lithography process to realize the passives with minimum possible feature size (<; 10 μm). A low cost insulating material, promising grafting solution and Laser assisted writing machine with optimized fabrication parameters are the highlights of this production method. A Computer Aided Design (CAD) software i.e. clewin is used during this process to pattern the mask for the entire process. Covalent bonded metallization (CBM) is the key process for the adhesion of copper layer on the desired site of the pattern. In the CBM process, a polymer surface is modified by grafting. The position of the surface modification is optically defined using a laser lithography system. Such surface modified samples are, then treated in an electroless copper process. Resulting in copper metallization only at the locations with a CBM modified surface. The verification of the copper deposition on the substrate is investigated using a high-resolution microscope followed by scanning electron microscopy (SEM). The confirmation of passive formation has been checked using kethley's source (electrical two-probe measurement). The first-order measured results showed the capacitance formed in the range of 0.3-8 pF. Further concrete measurements using standard methods are undergoing. One of the key advantage of this proposed process is its easiness and feasibility of at room temperature.

Place, publisher, year, edition, pages
IEEE, 2019.
Series
European Microelectronics and Packaging Conference, EMPC
Keywords [en]
CBM, additive process, embedded passives, grafting material, Urethane coat, LASER patterning, Electroless Copper Plating, SBU process, PCB
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electronic systems
Identifiers
URN: urn:nbn:se:ltu:diva-78689DOI: 10.23919/EMPC44848.2019.8951871ISI: 000532694100096Scopus ID: 2-s2.0-85078823665OAI: oai:DiVA.org:ltu-78689DiVA, id: diva2:1426652
Conference
2019 22nd European Microelectronics and Packaging Conference & Exhibition (EMPC), 16-19 September, 2019, Pisa, Italy
Note

ISBN för värdpublikation: 978-0-9568086-6-0, 978-1-7281-6291-1

Available from: 2020-04-27 Created: 2020-04-27 Last updated: 2022-11-02Bibliographically approved
In thesis
1. An SBU fully additive production approach for Board-level Electronics Packaging (SBU-CBM Method)
Open this publication in new window or tab >>An SBU fully additive production approach for Board-level Electronics Packaging (SBU-CBM Method)
2021 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

The worldwide electronics market is focusing on developing innovative technologies that can lead to denser, more resilient, and tighter board-level integration. The consumer electronics market is trending toward miniaturization, with HDI-PCBs dominating. Electronics shrinking and scaling technology is the prime concern of all manufacturers. The PCBA industry is transforming its production practices which can reduce the solder joints, limit the usage of discrete and bulky components, reduce the packaging factor of printed boards by accommodating the maximum number of ICs, minimize the assembly span, optimize the latency, and so on. However, developments in production processes in the PCB manufacturing industry need more attention than those in  Silicon-based (ICs) fabrications. One of the issues in PCB fabrication is utilizing conventional metallization approaches. The majority of manufacturers continue to use standard Copper(Cu) laminates on the base substrate and lithography methods to shape the structures.In recent manufacturing technologies, semi-Additive process (SAP) or modified-SAP (mSAP) methods are being adopted to replace traditional subtractive print-and-etch procedures. To scale down the Lines and Spaces (L\&S) on PCBs comparable to that of IC-level, most smartphone makers use Substrate-like PCB (SLP) using mSAP methods. However, subtractive patterning has been used in the intermediate stages of fabrication in those methods. This thesis demonstrates a fully additive selective metallization-based production approach to bridge this technology gap between IC-level and board-level fabrications. The fabrication process has given the name 'Sequential Build-Up Covalent Bonded Metallisation' (SBU-CBM) method.

This dissertation presents a new approach to Cu metallization using a significant step reducing-pattern-transfer process. The patterning method activates a seed layer of CBM polymer chains on a polymer surface with optimal UV-Laser settings. This surface modification enables a strong Copper (Cu) bonding onto the modified surface by Cu-plating. The suggested approach generated a 2.5D surface pattern using a micrometer via laser ablation and subsequent sub-micrometer laser lithography. Furthermore, the surface characterization of each step involved in the fabrication process is analysed and presented to show the sequential growth of layers on top of each other. To investigate the mechanism of the process at the interfaces, characterizations such as EDS, SEM, and XRD characterizations were performed. This PCB manufacturing method can selectively add metallic layers to the finest feature sizes at considerably lower temperatures. Overall, the thesis has addressed two critical aspects i.e. miniaturization of interconnects at board-level and the feasibility of a fully-additive production approach for electronics packaging.

First, a subtractive method is shown to achieve Copper interconnects with feature size 3.0$\mu$m. This miniaturization corresponds to 70\% reduction in the feature size from 20 $\mu$m to 3 $\mu$m. Next, the proposed additive production process has produced Cu interconnects with feature sizes of 2.5 $\mu$m L\&S and via of diameter 10 $\mu$m. The scaling of the interconnects was achieved by optimizing the process parameters involved in the proposed fabrication recipe.

Second, the sequential build-up (SBU) procedure is adopted to realize the embedded passives with the minimum possible feature size ($<$ 10 $\mu$m). An embedded capacitor and a planar inductor were fabricated. The proposed method can be employed to achieve any desirable pattern on FR-4, and a few of them are shown in the thesis. This additive technique can further be investigated through electrical and reliability assessment to make it an industrially accepted method.

Place, publisher, year, edition, pages
Luleå University of Technology, 2021
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Cyber-Physical Systems
Identifiers
urn:nbn:se:ltu:diva-88609 (URN)978-91-8048-001-7 (ISBN)978-91-8048-002-4 (ISBN)
Presentation
2022-02-25, E632, 10:00 (English)
Supervisors
Available from: 2021-12-30 Created: 2021-12-29 Last updated: 2022-02-10Bibliographically approved

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Acharya, SarthakChouhan, Shailesh SinghDelsing, Jerker

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