A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodesShow others and affiliations
2021 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 107, no 2, p. 339-352Article in journal (Refereed) Published
Abstract [en]
The work proposes an 11T SRAM cell which confirms its reliability for Internet of Things (IoT) based health monitoring system. The cell executes improved write and read ability using data-dependent feedback cutting and read decoupled access path mechanism respectively. The write and read stabilities of proposed cell are 2.67× and 1.98× higher than the conventional 6T cell with 1.53× area overhead. Moreover, the improved soft error tolerance and better reliability against negative bias temperature instability (NBTI) of proposed 11T SRAM cell as compared to other considered cells make it suitable for the bio medical implant. A low-power double adjacent bit error detection and correction (DAEDC) scheme is proposed to further improve the robustness of designed 1 Kb bit-interleaved memory against the soft error occurrence. The leakage power of proposed cell is controlled by the stacking devices used in its cross-coupled inverter pair and the column based read ground signal (RGND) further controls the unnecessary bit line switching power of the array.
Place, publisher, year, edition, pages
Springer, 2021. Vol. 107, no 2, p. 339-352
Keywords [en]
Static random access memory (SRAM), Stability, Half-select issue, Bit-interleaving, Soft error
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Cyber-Physical Systems
Identifiers
URN: urn:nbn:se:ltu:diva-81196DOI: 10.1007/s10470-020-01728-4ISI: 000575747000001Scopus ID: 2-s2.0-85092110833OAI: oai:DiVA.org:ltu-81196DiVA, id: diva2:1478368
Note
Validerad;2021;Nivå 2;2021-04-19 (johcin)
2020-10-222020-10-222021-04-19Bibliographically approved