System-on-chips (SoCs) for the Internet of things (IoT) applications require hardware-based integrated random number generators for the secure transmission of information. However, they have limited hardware and power budget, which limits the use of on-chip dedicated True Random Number Generator (TRNG). In this work, a symmetric D flip-flop with integrated TRNG is proposed. The proposed architecture is implemented using a standard 40 nm CMOS technology. The post-layout simulation results show that it offers good randomness with low energy-per-bit. In addition, the circuit has passed all the tests of NIST without any post-processing. When compared with the conventional D flip-flop, it has almost negligible area overhead that is only 0.14%. An FPGA implementation is also presented as a proof of concept that confirms the simulation results. Advanced Encryption Standard (AES) key expansion algorithm is also implemented to demonstrate the dual usage of the proposed D flip-flop.