Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Efficient RISCV Peripheral Access Through Library Level Instruction Selection in Rust
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Computer Science. Tampere University.
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Computer Science. Tampere University.
2024 (English)In: 2024 IEEE 3rd Industrial Electronics Society Annual On-Line Conference (ONCON), Institute of Electrical and Electronics Engineers Inc. , 2024Conference paper, Published paper (Refereed)
Abstract [en]

The open RISC-V instruction set architecture (ISA) defines a new era of domain-specific computer architectures by allowing the implementation of custom, application-specific instructions. In this paper, we propose a novel approach to exposing such instructions to the end user in the Rust programming language. The proposed approach discriminates between statically known and unknown values, and automatically emits the appropriate (e.g, immediate- or register to register-type) instruction without changes to the Rust toolchain. We validate the approach by implementing a Peripheral Access Crate (PAC) for the RISC-V Real-Time Hippomenes architecture. Hippomenes introduces CSR (Control and Status Register)-mapped peripherals allowing efficient peripheral access with reduced software overhead (single instruction read-write/set/clear, including 12-bit peripheral address and optional 5-bit immediate field). Our experiments confirm that all software abstraction layers introduced are completely eliminated at compile time. Moreover, for all cases where the LLVM compiler backend can deduce values to be statically known, immediate instruction variants are selected (thus improving performance and reducing register pressure in comparison to register instructions).

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc. , 2024.
Keywords [en]
embedded Rust, RISC-V, const evaluation, intrinsic
National Category
Computer Systems
Research subject
Dependable Communication and Computation Systems; Cyber Security
Identifiers
URN: urn:nbn:se:ltu:diva-112512DOI: 10.1109/ONCON62778.2024.10931739Scopus ID: 2-s2.0-105002241230OAI: oai:DiVA.org:ltu-112512DiVA, id: diva2:1954440
Conference
3rd IEEE Industrial Electronics Society Annual Online Conference (ONCON 2024), Beijing, China, [DIGITAL], December 8-10, 2024
Note

ISBN for host publication: 979-8-3315-4031-9;

Funder: ITEA 4 GenerIoT project; European Union (20366918);

Available from: 2025-04-24 Created: 2025-04-24 Last updated: 2025-04-24Bibliographically approved

Open Access in DiVA

No full text in DiVA

Other links

Publisher's full textScopus

Authority records

Lindgren, PerDzialo, Pawel

Search in DiVA

By author/editor
Lindgren, PerDzialo, Pawel
By organisation
Computer Science
Computer Systems

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 21 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf