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  • 1.
    Al-Dhaqm, Arafat
    et al.
    School of Computing, Faculty of Engineering, Universiti Teknologi Malaysia (UTM), Skudai 81310, Malaysia; Department of Computer Science, Aden Community College, Aden 999101, Yemen.
    Ikuesan, Richard A.
    Department of Cybersecurity and Networking, School of Information Technology, Community College Qatar, Doha 00974, Qatar.
    Kebande, Victor R.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Digital Services and Systems.
    Shukor, Razak
    School of Computing, Faculty of Engineering, Universiti Teknologi Malaysia (UTM), Skudai 81310, Malaysia.
    Ghabban, Fahad M.
    Information System Department, College of Computer Science and Engineering, Taibah University, Madina 42353, Saudi Arabia.
    Research Challenges and Opportunities in Drone Forensics Models2021In: Electronics, E-ISSN 2079-9292, Vol. 10, no 13, article id 1519Article, review/survey (Refereed)
    Abstract [en]

    The emergence of unmanned aerial vehicles (also referred to as drones) has transformed the digital landscape of surveillance and supply chain logistics, especially in terrains where such was previously deemed unattainable. Moreover, the adoption of drones has further led to the proliferation of diverse drone types and drone-related criminality, which has introduced a myriad of security and forensics-related concerns. As a step towards understanding the state-of-the-art research into these challenges and potential approaches to mitigation, this study provides a detailed review of existing digital forensic models using the Design Science Research method. The outcome of this study generated in-depth knowledge of the research challenges and opportunities through which an effective investigation can be carried out on drone-related incidents. Furthermore, a potential generic investigation model has been proposed. The findings presented in this study are essentially relevant to forensic researchers and practitioners towards a guided methodology for drone-related event investigation. Ultimately, it is important to mention that this study presents a background for the development of international standardization for drone forensics.

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  • 2.
    Bhat, Soha Maqbool
    et al.
    Department of Electrical and Electronics Engineering, Mahindra University, Hyderabad, 500043, India.
    Ahmed, Suhaib
    Department of Electronics and Communication Engineering, Baba Ghulam Shah Badshah University, Rajouri 185234, India.
    Bahar, Ali Newaz
    Department of Information and Communication Technology (ICT), Mawlana Bhashani Science and Technology University, Tangail, 1902, Bangladesh; Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, SK S7N5A9, Canada.
    Wahid, Khan A.
    Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, SK S7N5A9, Canada.
    Otsuki, Akira
    Luleå University of Technology, Department of Civil, Environmental and Natural Resources Engineering, Geosciences and Environmental Engineering. Facultad de Ingeniería y Ciencias, Universidad Adolfo Ibáñez, Diagonal Las Torres 2640, Peñalolén, Santiago, 7941169, Chile; Neutron Beam Technology Team, RIKEN Center for Advanced Photonics, RIKEN, Wako, 351-0198, Japan.
    Singh, Pooran
    Department of Electrical and Electronics Engineering, Mahindra University, Hyderabad, 500043, India.
    Design of Cost-Efficient SRAM Cell in Quantum Dot Cellular Automata Technology2023In: Electronics, E-ISSN 2079-9292, Vol. 12, no 2, article id 367Article in journal (Refereed)
    Abstract [en]

    SRAM or Static Random-Access Memory is the most vital memory technology. SRAM is fast and robust but faces design challenges in nanoscale CMOS such as high leakage, power consumption, and reliability. Quantum-dot Cellular Automata (QCA) is the alternative technology that can be used to address the challenges of conventional SRAM. In this paper, a cost-efficient single layer SRAM cell has been proposed in QCA. The design has 39 cells with a latency of 1.5 clock cycles and achieves an overall improvement in cell count, area, latency, and QCA cost compared to the reported designs. It can therefore be used to design nanoscale memory structures of higher order.

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  • 3.
    Chouhan, Shailesh Singh
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Halonen, Kari
    Department of Electronics and Nanoengineering, Aalto University, Espoo, Finland.
    A 40 nW CMOS-Based Temperature Sensor with Calibration Free Inaccuracy within ±0.6 ◦C2019In: Electronics, E-ISSN 2079-9292, Vol. 8, no 11, article id 1275Article in journal (Refereed)
    Abstract [en]

    In this study, a temperature equivalent voltage signal was obtained by subtracting output voltages received from two individual temperature sensors. These sensors work in the subthreshold region and generate the output voltage signals that are proportional and complementary to the temperature. Over the temperature range of −40 ∘" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C to +85 ∘" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C without using any calibration method, absolute temperature inaccuracy less than ±0.6 ∘" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C was attained from the measurement of five prototypes of the proposed temperature sensor. The implementation was done in a standard 0.18 μ" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">μ m CMOS technology with a total area of 0.0018 mm 2" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">2. The total power consumption is 40 nW for a supply voltage of 1.2 V measured at room temperature.

  • 4.
    Ciani, L.
    et al.
    Department of information Engineering, University of Florence, via di S. Marta 3, Florence, 50139, Italy.
    Guidi, G.
    Department of information Engineering, University of Florence, via di S. Marta 3, Florence, 50139, Italy.
    Patrizi, G.
    Department of information Engineering, University of Florence, via di S. Marta 3, Florence, 50139, Italy.
    Galar, Diego
    Luleå University of Technology, Department of Civil, Environmental and Natural Resources Engineering, Operation, Maintenance and Acoustics. Industry and Transport Division, Tecnalia Research and Innovation, Miñano, 01510, Spain.
    Condition-Based Maintenance of HVAC on a High-Speed Train for Fault Detection2021In: Electronics, E-ISSN 2079-9292, Vol. 10, no 12, article id 1418Article in journal (Refereed)
    Abstract [en]

    Reliability-centered maintenance (RCM) is a well-established method for preventive maintenance planning. This paper focuses on the optimization of a maintenance plan for an HVAC (heating, ventilation and air conditioning) system located on high-speed trains. The first steps of the RCM procedure help in identifying the most critical items of the system in terms of safety and availability by means of a failure modes and effects analysis. Then, RMC proposes the optimal maintenance tasks for each item making up the system. However, the decision-making diagram that leads to the maintenance choice is extremely generic, with a consequent high subjectivity in the task selection. This paper proposes a new fuzzy-based decision-making diagram to minimize the subjectivity of the task choice and preserve the cost-efficiency of the procedure. It uses a case from the railway industry to illustrate the suggested approach, but the procedure could be easily applied to different industrial and technological fields. The results of the proposed fuzzy approach highlight the importance of an accurate diagnostics (with an overall 86% of the task as diagnostic-based maintenance) and condition monitoring strategy (covering 54% of the tasks) to optimize the maintenance plan and to minimize the system availability. The findings show that the framework strongly mitigates the issues related to the classical RCM procedure, notably the high subjectivity of experts. It lays the groundwork for a general fuzzy-based reliability-centered maintenance method. 

  • 5.
    Huang, Xiaomei
    et al.
    School of Information Management, Jiangxi University of Finance and Economics, Nanchang 330013, China. School of Mathematics and Statistics, Jiangxi Normal University, Nanchang 330022, China.
    Liao, Guoqiong
    School of Information Management, Jiangxi University of Finance and Economics, Nanchang 330013, China.
    Xiong, Naixue
    Department of Mathematics and Computer Science, Northeastern State University, Tahlequah, OK 74464, USA.
    Vasilakos, Athanasios V.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Computer Science. School of Electrical and Data Engineering, University of Technology Sydney, New South Wales, NSW 2007, Australia. College of Mathematics and Computer Science, Fuzhou University, Fuzhou 350116, China.
    Lan, Tianming
    School of Information Management, Jiangxi University of Finance and Economics, Nanchang 330013, China.
    A Survey of Context-Aware Recommendation Schemes in Event-Based Social Networks2020In: Electronics, E-ISSN 2079-9292, Vol. 9, no 10, article id 1583Article in journal (Refereed)
    Abstract [en]

    In recent years, Event-based social network (EBSN) applications, such as Meetup and DoubanEvent, have received popularity and rapid growth. They provide convenient online platforms for users to create, publish, and organize social events, which will be held in physical places. Additionally, they not only support typical online social networking facilities (e.g., sharing comments and photos), but also promote face-to-face offline social interactions. To provide better service for users, Context-Aware Recommender Systems (CARS) in EBSNs have recently been singled out as a fascinating area of research. CARS in EBSNs provide the suitable recommendation to target users by incorporating the contextual factors into the recommendation process. This paper provides an overview on the development of CARS in EBSNs. We begin by illustrating the concept of the term context and the paradigms of conventional context-aware recommendation process. Subsequently, we introduce the formal definition of an EBSN, the characteristics of EBSNs, the challenges that are faced by CARS in EBSNs, and the implementation process of CARS in EBSNs. We also investigate which contextual factors are considered and how they are represented in the recommendation process. Next, we focus on the state-of-the-art computational techniques regarding CARS in EBSNs. We also overview the datasets and evaluation metrics for evaluation in this research area, and discuss the applications of context-aware recommendation in EBSNs. Finally, we point out research opportunities for the research community.

  • 6.
    Nafees, Naira
    et al.
    Department of Electronics and Communication Engineering, Shri Mata Vaishno Devi University, Katra 182320, India.
    Ahmed, Suhaib
    Department of Electronics and Communication Engineering, Shri Mata Vaishno Devi University, Katra 182320, India; Department of Electronics and Communication Engineering, Baba Ghulam Shah Badshah University, Rajouri 185234, India.
    Kakkar, Vipan
    Department of Electronics and Communication Engineering, Shri Mata Vaishno Devi University, Katra 182320, India.
    Bahar, Ali Newaz
    Department of Information and Communication Technology (ICT), Mawlana Bhashani Science and Technology University, Tangail, 1902, Bangladesh; Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, SK S7N5A9, Canada.
    Wahid, Khan A.
    Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, SK S7N5A9, Canada.
    Otsuki, Akira
    Luleå University of Technology, Department of Civil, Environmental and Natural Resources Engineering, Geosciences and Environmental Engineering. Facultad de Ingeniería y Ciencias, Universidad Adolfo Ibáñez, Diagonal Las Torres 2640, Santiago, 7941169, Chile; RIKEN Center for Advanced Photonics, RIKEN, Wako, 351-0198, Japan.
    QCA-Based PIPO and SIPO Shift Registers Using Cost-Optimized and Energy-Efficient D Flip Flop2022In: Electronics, E-ISSN 2079-9292, Vol. 11, no 19, article id 3237Article in journal (Refereed)
    Abstract [en]

    With the growing use of quantum-dot cellular automata (QCA) nanotechnology, digital circuits designed at the Nanoscale have a number of advantages over CMOS devices, including the lower utilization of power, increased processing speed of the circuit, and higher density. There are several flip flop designs proposed in the literature with their realization in the QCA technology. However, the majority of these designs suffer from large cell counts, large area utilization, and latency, which leads to the high cost of the circuits. To address this, this work performed a literature survey of the D flip flop (DFF) designs and complex sequential circuits that can be designed from it. A new design of D flip flop was proposed in this work and to assess the performance of the proposed QCA design, an in-depth comparison with existing designs was performed. Further, sequential circuits such as parallel-in-parallel-out (PIPO) and serial-in-parallel-out (SIPO) shift registers were designed using the flip flop design that was put forward. A comprehensive evaluation of the energy dissipation of all presented fundamental flip-flop circuits and other sequential circuits was also performed using the QCAPro tool, and their energy dissipation maps were also obtained. The suggested designs showed lower power dissipation and were cost-efficient, making them suitable for designing higher-power circuits.

  • 7.
    Nilsson, Joakim
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Imperial Coll, Dept Phys, London SW7 2AZ, England.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Maximal Q Factor for an On-Chip, Fuse-Based Trimmable Capacitor2019In: Electronics, E-ISSN 2079-9292, Vol. 8, no 1, article id 62Article in journal (Refereed)
    Abstract [en]

    This paper presents a circuit for realising a fuse-programmable capacitor on-chip. The trimming mechanism is implemented using integrated circuit fuses which can be blown in order to lower the resulting equivalent capacitance. However, for integrated circuits, the non-zero fuse resistance for active fuses and finite fuse resistance for blown fuses limit the Q factor of the resulting capacitor. In this work, we present a method on how to arrange the fuses in order to achieve maximal worst-case Q factor for the given circuit topology given the process parameters and requirements on capacitance. We also analyse and discuss the accuracy and limitations of the topology with regard to fuse resistance and parasitic elements such as bond pads.

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  • 8.
    Seyedi, Saeid
    et al.
    Islamic Azad Univ, Urmia Branch, Young Researchers & Elite Club, Orumiyeh 5716963896, Iran; Islamic Azad Univ, Dept Comp Engn, Tabriz Branch, Tabriz 5157944533, Iran.
    Navimipour, Nima Jafari
    Natl Yunlin Univ Sci & Technol, Future Technol Res Ctr, Touliu, Yunlin 64002, Taiwan.
    Otsuki, Akira
    Luleå University of Technology, Department of Civil, Environmental and Natural Resources Engineering, Geosciences and Environmental Engineering. Facultad de Ingeniería y Ciencias, Universidad Adolfo Ibáñez, Diagonal Las Torres 2640, Peñalolén, Santiago 7941169, Chile; Neutron Beam Technology Team, RIKEN Center for Advanced Photonics, Wako 351-0198, Japan.
    A New Nano-Scale and Energy-Optimized Reversible Digital Circuit Based on Quantum Technology2022In: Electronics, E-ISSN 2079-9292, Vol. 11, no 23, article id 4038Article in journal (Refereed)
    Abstract [en]

    A nano-scale quantum-dot cellular automaton (QCA) is one of the most promising replacements for CMOS technology. Despite the potential advantages of this technology, QCA circuits are frequently plagued by numerous forms of manufacturing faults (such as a missing cell, extra cell, displacement cell, and rotated cell), making them prone to failure. As a result, in QCA technology, the design of reversible circuits has received much attention. Reversible circuits are resistant to many kinds of faults due to their inherent properties and have the possibility of data reversibility, which is important. Therefore, this research proposes a new reversible gate, followed by a new 3 x 3 reversible gate. The proposed structure does not need rotated cells and only uses one layer, increasing the design's manufacturability. QCADesigner-E and the Euler method on coherence vector (w/energy) are employed to simulate the proposed structure. The 3 x 3 reversible circuit consists of 21 cells that take up just 0.046 mu m(2). Compared to the existing QCA-based single-layer reversible circuit, the proposed reversible circuit minimizes cell count, area, and delay. Furthermore, the energy consumption is studied, confirming the optimal energy consumption pattern in the proposed circuit. The proposed reversible 3 x 3 circuit dissipates average energy of 1.36 (eV) and overall energy of 1.49 (eV). Finally, the quantum cost for implementing the reversible circuits indicates a lower value than that of all the other examined circuits.

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  • 9.
    Seyedi, Saeid
    et al.
    Young Researchers and Elite Club, Urmia Branch, Islamic Azad University, Urmia 57169-63896, Iran.
    Navimipour, Nima Jafari
    Future Technology Research Center, National Yunlin University of Science and Technology, Douliou, Yunlin 64002, Taiwan.
    Otsuki, Akira
    Luleå University of Technology, Department of Civil, Environmental and Natural Resources Engineering, Geosciences and Environmental Engineering. Ecole Nationale Supérieure de Géologie, GeoRessources UMR 7359 CNRS, University of Lorraine, 2 Rue du Doyen Marcel Roubault, BP 10162, 54505 Vandoeuvre-lès-Nancy, France; Neutron Beam Technology Team, RIKEN Center for Advanced Photonics, RIKEN, Wako, Saitama 351-0198, Japan.
    Design and Analysis of Fault-Tolerant 1:2 Demultiplexer Using Quantum-Dot Cellular Automata Nano-Technology2021In: Electronics, E-ISSN 2079-9292, Vol. 10, no 21, article id 2565Article in journal (Refereed)
    Abstract [en]

    Quantum-dot Cellular Automata (QCA) is an innovative paradigm bringing hopeful applications in the perceptually novel computing layout in quantum electronics. The circuits manufactured by QCA technology can provide a notable decrease in size, rapid-switching velocity, and ultra-low power utilization. The demultiplexer is a beneficial component to optimize the whole process in any logical design, and therefore is very important in QCA. Moreover, fault-tolerant circuits can improve the reliability of digital circuits by redundancy. Hence, the present investigation illustrates a novel QCA-based fault-tolerant 1:2 demultiplexer construct that employs a two-input AND gate and inverter. The functionality of the suggested layout was executed and evaluated with the utilization of the QCADesigner 2.0.3 simulator. This paper utilizes cell redundancy on the wire, inverter, and AND gates for designing a fault-tolerant demultiplexer. Four components (i.e., missing cells, dislocation cells, extra cells, and misalignment) were analyzed by the QCADesigner simulator. The simulation results demonstrated that our proposed QCA-based fault-tolerant 1:2 demultiplexer acted more efficiently than prior constructs regarding delay and fault tolerance. The proposed fault-tolerant 1:2 demultiplexer could attain high fault-tolerance when single missing cell or extra cell faults exist in the QCA layout.

  • 10.
    Seyedi, Saeid
    et al.
    Young Researchers and Elite Club, Urmia Branch, Islamic Azad University, Urmia 57169-63896, Iran.
    Otsuki, Akira
    Luleå University of Technology, Department of Civil, Environmental and Natural Resources Engineering, Geosciences and Environmental Engineering. Ecole Nationale Supérieure de Géologie, GeoRessources UMR 7359 CNRS, University of Lorraine, 2 Rue du Doyen Marcel Roubault, BP 10162, 54505 Vandoeuvre-lès-Nancy, France; Neutron Beam Technology Team, RIKEN Center for Advanced Photonics, RIKEN, Wako, Saitama 351-0198, Japan.
    Navimipour, Nima Jafari
    Future Technology Research Center, National Yunlin University of Science and Technology, Douliou, Yunlin 64002, Taiwan.
    A New Cost-Efficient Design of a Reversible Gate Based on a Nano-Scale Quantum-Dot Cellular Automata Technology2021In: Electronics, E-ISSN 2079-9292, Vol. 10, no 15, article id 1806Article in journal (Refereed)
    Abstract [en]

    Quantum-dot cellular automata (QCA) nanotechnology is a practical suggestion for replacing present silicon-based technologies. It provides many benefits, such as low power usage, high velocity, and an extreme density of logic functions on a chip. In contrast, designing circuits with no waste of information (reversible circuits) may further reduce energy losses. The Feynman gate has been recognized as one of the most famous QCA-based gates for this purpose. Since reversible gates are significant, this paper develops a new optimized reversible double Feynman gate that uses efficient arithmetic elements as its key structural blocks. Additionally, we used several modeling principles to make it consistent and more robust against noise. Moreover, we examined the suggested model and compared it to the previous models regarding the complexity, clocking, number of cells, and latency. Furthermore, we applied QCADesigner to monitor the outline and performance of the proposed gate. The results show an acceptable improvement via the designed double Feynman gate in comparison to the existing designs. Finally, the temperature and cost analysis indicated the efficiency of the proposed nan-scale gate.

  • 11.
    Ullah, Salim
    et al.
    Department of Computer Software Engineering, University of Engineering and Technology, Mardan 23200, Pakistan.
    Khan, Muhammad Sohail
    Department of Computer Software Engineering, University of Engineering and Technology, Mardan 23200, Pakistan.
    Lee, Choonhwa
    Department of Computer Science and Engineering, Hanyang University, Seoul 04763, Korea.
    Hanif, Muhammad
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Digital Services and Systems.
    Understanding Users’ Behavior towards Applications Privacy Policies2022In: Electronics, E-ISSN 2079-9292, Vol. 11, no 2, article id 246Article in journal (Refereed)
    Abstract [en]

    Recently, smartphone usage has increased tremendously, and smartphones are being used as a requirement of daily life, equally by all age groups. Smartphone operating systems such as Android and iOS have made it possible for anyone with development skills to create apps for smartphones. This has enabled smartphone users to download and install applications from stores such as Google Play, App Store, and several other third-party sites. During installation, these applications request resource access permissions from users. The resources include hardware and software like contact, memory, location, managing phone calls, device state, messages, camera, etc. As per Google’s permission policy, it is the responsibility of the user to allow or deny any permissions requested by an app. This leads to serious privacy violation issues when an app gets illegal permission granted by a user (e.g., an app might request for granted map permission and there is no need for map permission in the app, and someone can thereby access your location by this app). This study investigates the behavior of the user when it comes to safeguarding their privacy while installing apps from Google Play. In this research, first, seven different applications with irrelevant permission requests were developed and uploaded to two different Play Store accounts. The apps were live for more than 12 months and data were collected through Play Store analytics as well as the apps’ policy page. The preliminary data analysis shows that only 20% of users showed concern regarding their privacy and security either through interaction with the development team through email exchange or through commenting on the platform and other means accordingly.

  • 12.
    Vahabi, Mohsen
    et al.
    Department of Electrical Engineering, Islamic Azad University of Science and Research Tehran (Kerman) Branch, Kerman 7718184483, Iran.
    Bahar, Ali Newaz
    Department of Information and Communication Technology (ICT), Mawlana Bhashani Science and Technology University, Tangail 1902, Bangladesh; Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, SK S7N 5A9, Canada.
    Otsuki, Akira
    Luleå University of Technology, Department of Civil, Environmental and Natural Resources Engineering, Geosciences and Environmental Engineering. Facultad de Ingeniería y Ciencias, Universidad Adolfo Ibáñez, Diagonal Las Torres 2640, Peñalolén, Santiago 7941169, Chile; RIKEN Center for Advanced Photonics, RIKEN, Wako 351-0198, Saitama, Japan.
    Wahid, Khan A.
    Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, SK S7N 5A9, Canada.
    Ultra-Low-Cost Design of Ripple Carry Adder to Design Nanoelectronics in QCA Nanotechnology2022In: Electronics, E-ISSN 2079-9292, Vol. 11, no 15, article id 2320Article in journal (Refereed)
    Abstract [en]

    Due to the development of integrated circuits and the lack of responsiveness to existing technology, researchers are looking for an alternative technology. Quantum-dot cellular automata (QCA) technology is one of the promising alternatives due to its higher switch speed, lower power dissipation, and higher device density. One of the most important and widely used circuits in digital logic calculations is the full adder (FA) circuit, which actually creates the problem of finding its optimal design and increasing performance. In this paper, we designed and implemented two new FA circuits in QCA technology and then implemented ripple carry adder (RCA) circuits. The proposed FAs and RCAs showed excellent performance in terms of QCA evaluation parameters, especially in cost and cost function, compared to the other reported designs. The proposed adders’ approach was 46.43% more efficient than the best-known design, and the reason for this superiority was due to the coplanar form, without crossovers and inverter gates in the designs.

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