This paper presents a background and an overview of the initial design considerations for phased array antenna being designed for the New Generation multi-static, incoherent-scatter radar station - EISCAT-3D - in Northern Scandinavia. Its anticipated electrical, mechanical and environmental design requirements are given both by the physics as well as by the extreme climate in the subarctic region of northern Scandinavia
We present an ultrasonic transducer interface IC that includes an 8-bit, 40 V pp , 400 mA current output DAC for arbitrary waveform transducer excitation and a ±25 V analog multiplexer. The IC was fabricated using a 0.35 μm, 50 V CMOS process. The design eliminates the need for an external power amplifier as the piezoelectric transducer is driven directly from a segmented push-pull current output DAC, which simplifies the overall system design. This approach has the advantage of simple and rapid glitch-free power-up/down, which is especially important in integrated high-output-power drivers. The DAC has been evaluated when operating at a 150 MHz sampling rate with a ±400 mA output current and a 50 Ω load. Measured performance includes 37 dB SNDR and 46 dB SFDR at 10 MHz output frequency. By implementing an additional reference DAC and extending the receiver isolation switch into an analog multiplexer, we enable on-line calibration for the purpose of reducing the driver and receiver signal path uncertainty. Measurements show a greater than ten-fold improvement in delay uncertainty to approximately 20 ps for temperature variations of 0 to 70 degrees Celsius.
Efficient beamforming of phased-array antennas requires that the phase delay of each channel is accurately known. One technique for achieving this is to distribute a calibration or local-oscillator reference signal through a delay-insensitive signal distribution network. In this paper, we propose using passive hierarchical signal distribution networks to distribute such signals, a method that scales significantly better with the size of the array than existing signal distribution methods. We analyze the impact of impedance variations within the network on the phase accuracy and propose a calibration front-end architecture. This front end also enables the return loss and coupling between antennas to be monitored for diagnostic purposes. We present an implementation of this front end that was applied to a small prototype antenna array, and show that this implementation exhibited low sensitivity to delays within the calibration network, reduced the temperature-dependent phase error of the front ends substantially, and can be used for performing antenna return-loss measurements
This paper presents measurements on a surfacechannel CCD with gates implemented using single-layer polysilicongates. The device was manufactured in a 0.18 μm PINNEDphoto diode CMOS process commercially available from UMC.The CCD was built with a field-plate covering all gates as wellas the space between them, which allows the potential in the gapbetween non-overlapping gates to be manipulated.We present charge transfer efficiency measurements performedat clock frequencies of 1 MHz and 5 MHz, at multiplebackground packet sizes, and field-plate voltages. We furtherpropose and apply a method for separating CTI in four-phaseCCDs due to trapping from the inefficiency stemming from otherphenomena.The measurements show a single stage CTI ranging from 1.7×10−4 with a moderate background charge and substantial fieldplatevoltage, to 0.007 at zero field-plate voltage and the highestbackground charge tested. The CTI can be reduced significantly(more than a factor of 10 in some cases) by applying a significantnegative voltage at the field-plate. This, and the fact that only aminor part of the CTI can be attributed to trapping, indicatesthat the performance of the device is limited by the presence ofpotential hollows in the gaps between the gates.
Traditionally BJT or BiCMOS amplifiers have been used to achieve equivalent input noise densities of 1 nV√Hz or less, as desirable in some ultrasonic applications. Due to an increasing demand on increased integration it can be necessary to implement the amplifier in a CMOS process. As part of this design process we applied the particle swarm optimization to the problem of optimizing an amplifier specifically for operation in the 2-4 MHz frequency band. We present measurements on the manufactured circuit with performance comparable to the best available BJT-based amplifiers available today.
Ultrasonic transit-time flow-meters estimate fluid or gas flows from the difference in times of flight of upstream and downstream acoustic pulses. However, any delay differences arising from sources other than the flow to be measured will cause a troublesome "zero flow" offset error.In theory, the transducers used in the measurement system should not influence the zero flow error, as electroacoustic systems based on piezoelectric transducers have been shown to be reciprocal (when the media is stationary). However, care is required when designing the electrical interfaces for the piezoelectric transducers, if reciprocity in the system is to be utilized.This work presents technique and measurements that apply reciprocity to an ultrasonic transit-time flow-meter. Specialized electrical transducer interfaces with options to drive the transducers from either low or high impedance sources were used. Combined with a high-impedance receive mode these options made it possible to change the conditions for reciprocity in the system.We show reduced delay difference in 9 cases out of 10 when trying to utilize the reciprocal property compared to when we disregard it in favor for larger excitation energy. The delay improvements were accompanied by reduced differences between the center frequencies of the signals from the two paths.
When discussing powering wireless sensor network nodes, there are a few major energy consumers: communications, microcontroller and the sensor. We propose a wireless sensor network platform architecture minimizing the energy consumption of sensing. The architecture proposed herein is based on a reactive approach to sensing. A number of possible hardware approaches are evaluated and compared. This comparison indicates that analog storage between the sensing element and the sensor electronics can be a feasible method for reducing the energy consumption of the system.
When discussing powering wireless sensor net- work nodes, there are a few major energy consumers: com- munications, microcontroller and the sensor. We propose a wireless sensor network platform architecture minimizing the energy consumption of sensing. The architecture proposed herein is based on a reactive approach to sensing. A number of possible hardware approaches are evaluated and compared. This comparison indicates that analog storage between the sensing element and the sensor electronics can be a feasible method for reducing the energy consumption of the system.
It is reasonable to think that sensor networks might be part of society critical systems in the future. Therefor this paper discusses and shows the vulnerabilities of sensor networks to intentional electromagnetic interference (IEMI). Principle ways of sensor network IEMI is addressed and followed by a discussion on schemes for protection. Experimental results for both in-band and exband interference from low- and high- level sources is reported. It is obvious that more emphasis has to be put on sensor networks susceptibility to IEMI, and in particular more experimental data is needed.
This paper presents the technology concepts for a “thumb”-sized self-contained ultrasonic IoT measurement sys- tem. An overall architecture is proposed, and key elements are discussed with solutions using existing technology, thus arguing that realization is possible with the current technology.
Such an ultrasonic IoT measurement system is constrained by its size and available energy, although it requires at least decent computational and communication resources. Because streaming data from such a device is not advisable from an energy viewpoint, there is a need for resource efficient (energy, memory and computational power) data analysis.
An architecture with the following parts as well as some implementation details and performance data are proposed here:
Energy supply, battery and super capacitor
Transducer excitation achieving almost zero electrical losses
Event detection sensor interface
Data aggregation using sparse approximation and learned
feature dictionaries, adapted to resource constrained em-
bedded systems
IoT communication protocols and implementations enabling
event -based communication and System of Systems integra- tion capabilities
The optimization of system level performance requires each subsystem to be optimized for the specific measurement situation taking into account the subsystem interdependencies. This can be performed using a combined electrical and acoustical model of the system. Here, the model allowing electronic and acoustic co-simulation using SPICE is an important tool bridging the electronic and acoustic domains.
This paper describes the design and impementation of an integrated frontend for electrocardiographic (ECG) systems, realized in a 0.35 μm 2P4M CMOS process. The performance is optimized to adhere to the standard IEC60601-2-47, which defines the requirements for safety and essential performance of ambulatory ECG equipment. The system consists of three channels to measure the 3 leads of a Goldberger ECG monitoring scheme, therefore a single ended design structure was chosen to minimize the power consumption. A fourth channel is included for additional measurements. Each of the four channels contains a low power multi-bit sigma-delta modulator and a low power digital filter. Three channels are equipped with a low noise preamplifier. The supply voltage can be varied from 2.4 Volt up to 3.6 Volt. With a total power consumption of less than 2 mW the circuit is designed for battery operated equipment.
Vid dödnätstart av produktionsanläggningar och drift av svaga nät eller ö-drift är frekvensomriktare som driver pumpar och fläktar kritiska komponenter. Om frekvensomriktare påverkas av störningar i nätet kan elproduktion kopplas bort och det svaga nätet eller ö-driften kollapsa. Projektet ska studera frekvensomriktare ur ett antal aspekter såsom uppbyggnad, styrning och implementering i syfte att utveckla mer robusta frekvensomriktare och implementering av dessa för att säkerställa drift av svaga nät och ö-drift och minimera ytterligare driftstörningar vid svåra påfrestningar på elnätet.
This paper analyses the frequency limitations of an active rectifier for RFID applications that has been optimised for 13.56 MHz. The rectifier utilises an active MOS diode with threshold cancellation and a control scheme to reduce reverse leakage. The rectifier is implemented in AMS 0.35 µm CMOS and simulated in Cadence Spectre. For an input voltage of 2 V and an output current of 20 µA, a power and voltage conversion efficiency of 83 % and 89 %, respectively, are achieved at 13.56 MHz. We show that reducing the width of the main MOS transistor from 90 to 60 µm improves the upper frequency limit, but beyond 30 MHz the finite speed of the threshold cancellation control circuit limits the efficiency of the rectifier circuit.
Outdoor applications of electronics modules expose the systems to harsh environmental conditions. When very high performance is required, it may be necessary to actively stabilize the temperature in the module. This paper presents a systematic approach to the problem of designing a temperature stabilized environment for medium size electronics modules. The target system is the front-end electronics for the antennas in the EISCAT-3D incoherent scatter radar system. The electronics have an estimated constant power dissipation of about 10 W. Initially simulations verified the design approach and gave valuable information of the heat distribution in the box over the range of target temperatures. The design was evaluated by making a prototype on which different measurements were performed, which gave a clear picture of the system functionality. Using two Peltier modules and an insulated box a temperature stability of ±0.02°C at 20°C over an ambient temperature range of -40°C to 40°C was achieved.
A relative ultrasound energy estimation circuit has been designed in a standard 0.35-μm CMOS process, to be a part of a thumb size internet connected wireless ultrasound measurement system. This circuit measures the relative energy between received ultrasound pulses, and presents an output signal that is linear to the received energy. Post-layout simulations indicate 7 bit linearity for 500 mV input signals, 5 μsec startup and stop times, 2.6 mW power consumption during active state. The active area measures 0.6 mm2 including digital logic, bias generation, and an on-chip oscillator. The circuit has been sent for manufacturing in the austrianmicrosystems C35B4 process via Europractice MPW.
This paper investigates how a power efficient customized front-end for a piezoelectric crystal can be designed. The specification and requirements of the front end are analyzed, and a sample design is presented. The sample design show 20 dB gain at 10 MHz, a current consumption of 1.7 mA with 9.2 nV/√Hz equivalent input noise, and a start-up time of 5 μs.
This paper presents simulations and methods developed to investigate the feasibility of using a Fractional-Sample-Delay (FSD) system in the planned EISCAT_3D incoherent scatter radar. Key requirements include a frequency-independent beam direction over a 30 MHz band centered around 220 MHz, with correct reconstruction of pulse lengths down to 200 ns. The clock jitter from sample to sample must be extremely low for the integer sample delays. The FSD must also be able to delay the 30 MHz wide signal band by 1/1024th of a sample without introducing phase shifts, and it must operate entirely in baseband. An extensive simulation system based on mathematical models has been developed, with inclusion of performance-degrading aspects such as noise, timing error, and bandwidth. Finite Impulse Response (FIR) filters in the baseband of a band-pass-sampled signal have been used to apply true time delay beamforming. It has been confirmed that such use is both possible and well behaved. The target beam-pointing accuracy of 0.06° is achievable using optimized FIR filters with lengths of 36 taps and an 18 bit coefficient resolution. Even though the minimum fractional delay step necessary for beamforming is ∼13.1 ps, the maximum sampling timing error allowed in the array is found to be σ ≤ 120 ps if the errors are close to statistically independent.
While developing the timing system for the receiver arrays for the EISCAT_3D system, several approaches to detect and adjust for timing errors within the array have been explored. The demand on the timing error between all elements in the array is to have a standard deviation of less than 120 ps, thus requiring high quality error detection systems to guarantee radar operation. This paper investigates the qualities of a secondary error detection system based on statistical analysis of captured data. The measurements are assembled with a Signal-to-Noise Ratio (SNR) of -30 dB implying that the elements in a 2112 element array need to be grouped into sub-arrays of 48 elements each. The captured data is then evaluated by Principal Component Analysis (PCA) and averaged over 20,000 measurements, or about half a second. Timing errors between sub-arrays of down to ~120 ps and a percentage of faulty sub-arrays of up to 20% are detectable. As a secondary error detection system PCA is cheap to implement since the only need of the analysis is a small amount of computer time. It also provides a valuable detection system for hardware errors in the primary timing system that can otherwise be hard to find.
Sammanfattningsvis är forskningsmålet att optimera kretskortsproduktion för små och medelstora serier. Huvudsakligen handlar det om att undersöka och modellera det termiska systemet mellan kretskort och lödugn. Modellen kommer sedan att användas för att ge bättre konfigurationsparametrar för produktionslinjen. En bra modell kommer inte bara att öka lödningskvalitén och minska antalet kasserade kretskort men kan också även användas för att hitta avvikelser redan i kretskortsdesignen.
This thesis presents building blocks and strategies to reach the goal of a thumb-size autonomous ultrasound measurement system with wireless communication capabilities. The design of modern electronics is based on the possibility to accurately predict system behavior by the use of simulation tools. This paradigm can be extended to components such as sensors attached to the electronics. The ability to simulate mechanical components and electronics together renders possible effective optimization at system level, i.e. minimizing size, cost and power consumption. All of these parameters are important for measurement systems aiming at the rapidly growing field of sensor networking and ambient intelligence. The work in this thesis connects the mechanics of piezoelectric transducers with the design of on-chip microelectronics. Throughout the work, SPICE models of the ultrasound system are used within the design tool for integrated circuits. Improvements and verifications of existing SPICE models for ultrasound equipment is described and applied in the design of integrated electronics for an ultrasound measurement system. The overall aim has been to achieve minimal system size and power consumption through interdisciplinary work based on knowledge within both ultrasonics and electronics. The thesis is divided into introductional chapters and eight attached papers. The introductional chapters give an overview of ultrasound devices, measurement technology, and simulation models. Tools and design flow for analog and mixed signal integrated circuits are discussed. Finally, an overview of the electronics in a pulse-echo ultrasound system is given. The attached papers cover various topics required to reach the goals presented above. The first three papers are closely related to the SPICE models of the piezoelectric devices and the ultrasound propagation media. First, a design strategy towards an area optimized driver stage for piezoelectric crystals with the help of SPICE simulations is presented. A prototype chip design has been made and it is shown that simulations and measured performance agree well. Second, diffraction loss for ultrasound pulses is included in the SPICE models for the ultrasound propagation medium. It is shown that this enables accurate simulations of absolute amplitudes in a pulse-echo ultrasound system with its associated electronics. Third, the influence of parasitic components stemming from cabling in the system are simulated and shown to agree well with measured data. Analog to digital converters and comparators are useful components in a pulse echo ultrasound system. The design of these blocks with focus on low power consumption is presented in two papers. The fourth paper presents a low power, high resolution sigma delta A/D converter, while the fifth paper introduces the deign of a delay-time stable time-continuous comparator suitable for use in time quantization A/D converters. The last three papers address three aspects of system level design of the ultrasound measurement system. The sixth paper presents the mounting of the electronics chip directly onto the piezoelectric crystal using wire bond technology. The setup enables precise pulse control and results in a very compact design. The seventh paper discusses the design of a complete embedded internet system (EIS) confined in the space 25x23x5 mm^3. The system incorporates an integrated web server, Bluetooth communication, and TCP/IP stack and is intended to serve as a base for Internet connected sensors. Finally, the eighth paper introduces a complete on-chip solution for the transmission and reception of ultrasound pulses with a piezoelectric crystal. The chip is designed in a high voltage process, and incorporates an inductive boost pump to achieve a high voltage for the excitation of the crystal. An integrated amplifier is used to amplify incoming pulses. The chip is controlled by a digital state machine used to achieve intermittent operation of the amplifier for minimum power consumption.
Using SPICE, successful efforts have previously been made in modeling piezoelectric devices and their functionality. In this paper the piezoelectric device is simulated together with MOS transistor models. The design of a CMOS piezoelectric crystal driver stage is presented. Measurements on a manufactured chip verify the chosen design approach and the performance predicted by the simulations. In the work, achieving small silicon area while maintaining maximum possible output ultrasound pulse amplitude has been a key criterion. The driver stage has been implemented using a 0.6 μm CMOS process. Measurements and simulations have been performed using PZ-27 crystals without backing. Results clearly show that the performance of a complete system comprising both piezoelectric and electronical devices can be predicted with good accuracy using the proposed SPICE simulation approach.
The success of modern electronics is built on the possibility to accurately predict system behavior by the use of simulation tools. This paradigm can be extended to components such as sensors attached to the electronics. The ability to simulate both sensors (mechanical components) and electronics together renders possible effective optimizations at system level, i.e. minimizing size, cost and power consumption. In this thesis the simulation of a combined electronics and ultrasound sensor system is explored. The environment used is compatible with the electronic simulation tool SPICE. Improvements and verifications of existing SPICE models for ultrasound equipment is described, and applied in the design of integrated analog electronics for an ultrasound measurement system. Emphasis is put on the interdependence between acoustic performance and electronics design. The goal is to improve precision in the simulations to a level where real systems can be implemented from simulation results alone. The thesis is divided into introduction and three attached papers. In the introduction, an overview of ultrasound devices, measurement technology and simulation is given. Tools and design flow for analog integrated circuits are discussed. The first paper shows that system simulations can be used to minimize the size of the transistors used to excite an ultrasound transducer, while keeping maximum output ultrasound energy. A design of an ASIC (Application Specific Integrated Circuit) driver stage for piezoelectric crystals is made and performance of the system is predicted using system simulations. Measurements and simulations are compared, showing that the optimum transistor size can be chosen from simulation data with very good precision. The goal with paper number two is to achieve absolute amplitude correctness in PSpice simulations of ultrasonic systems. Previously published models of the ultrasound propagation medium include viscoelastic loss but disregard loss due to diffraction, i.e. beam spreading. This paper presents a method to include diffraction loss in the models. Measurements and simulations have been performed using a pulse echo system in water. Results show that the simulated amplitude of the returned echo differs less than 10% from measured values in both near and far fields. In paper number three, the influence of parasitic electrical components on measurements and simulations is investigated. It is shown that simulation of excitation pulses can be done with very high accuracy if parasitics are taken into account. The coaxial cable which connects the electronics and the transducer represents one of the major parasitic components in the system. As the cable length is varied, pulse echo amplitudes and time delays shift. It is shown that simulations can be used to predict these effects with good accuracy.
This paper presents an encapsulation concept that enables the construction of small wireless measurement systems that can operate in industrial environments with ambient temperatures of up to 1200°C. To maximize operational time and minimize size, a layer of thermal insulation is combined with water absorbed in a porous material in the core of the device. The simulated operating time before all of the frozen water at 0?C has transformed into steam at 100°C when the ambient temperature of the device was 1200°C is 21 minutes for a sphere with an outer radius of 4 cm. If the outer radius is increased to 10 cm the simulated operating time increases to 125 minutes. Measurements were performed to validate the design. When a sphere with a radius of 4 cm was subjected to an oven temperature of 1200°C the device held the core temperature at or below 101°C for a total of 25 minutes. The time to reach the boiling point of the water was 9 minutes. Thereafter, the temperature was held constant at 100 +/- 1°C for an additional 16 minutes whereafter a rapid rise in temperature took place once all water had evaporated.
SPICE models of a piezoelectric device and the ultrasound propagation medium can be used in a simulator intended for electronic circuits and IC design to make efficient system level optimizations. This paper presents the inclusion of mechanical noise in the SPICE model of an ultrasound system. The modeling of the noise is based on the mechanical thermal noise which is equivalent to electronic Johnson (thermal) noise. For a system with a high-Q piezoelectric device designed into a medium-Q transducer the main energy loss, and thus also the main noise contribution, will occur in backing and sound propagation media. Thus, the modeling of the mechanical noise is performed by including electrical noise generation in the resistors that model these media in the electrical equivalent circuit. The resulting output voltage noise follows theoretical derivations of transducer noise as published by Farlow and Hayward. Simulations of a 4 MHz Pz27 piezoelectric disc with a diameter of 8 mm give a peak spectral noise density over 1 nV / √Hz, which is comparable to that achievable with low-noise preamplifiers.
The integration of sensor and electronics is important to reduce size, cost and power consumption for a measurement system. Sensors based on piezoelectric ceramic materials traditionally have a low degree of sensor and electronics integration. This paper describes the design of a highly integrated ultrasound transmit/receive unit where the piezoceramic sensor is used as the carrier for the driver electronics. An optimized ASIC driver stage in bare die format and two lithium battery cells which give 6 V supply voltage are glued directly to the back side of the sensor. Electrical connections are made from the driver stage to the crystal using wire bond technology. Measurements have been performed with an air backed crystal and Plexiglas as the medium. The absence of long wiring and parasitic components between the driver stage and the driven crystal give excellent pulse control possibilities. The power consumption of the driver stage/crystal combination is linearly dependant on the repetition rate, with a current consumption of less than 20 μA at 1 kHz repetition rate. The approach taken introduces issues regarding the influence of vibrations in the MHz-range on die attachment and wire bonding connections, which need to be further investigated.
When driver and receiver electronics for an ultrasound measurement system are physically implemented, parasitic components are introduced in the system. These may arise from bond wires, circuit board paths or cabling. The parasitic components will influence the excitation pulse behavior as well as amplitude and time of arrival for received pulses. In the system investigated, a coaxial cable is used to connect the transducer with the electronics. The inductance and capacitance of the cable are dominating parasitic components in the system. This paper investigates the effects of these components for varying cable lengths and compares measurements with system simulations using SPICE models. The simulations give highly accurate temporal behavior of the excitation pulse. The peak to peak amplitude and the perceived time of flight of the received echo in a pulse echo system is measured. Amplitude variations of 60% are recorded for cable lengths varied between 0.07 m and 2.3 m., with simulations predicting the same variations. The time of flight is measured using the excitation pulse as time trigger. Variations are up to 40 ns for a total travel time of about 8 µs. The simulations predict this variation within a few ns.
This paper reports on investigations of the electrical energy needed to generate ultrasound pulses with piezoelectric crystals and compares measurements with system simulations using SPICE models. The piezoelectric device used is a 16 mm diameter Pz27 crystal with a nominal resonance frequency f/sub oos,nom/ of 4.4 MHz. An optimized ASIC driver stage with 5 V supply voltage is mounted directly on the piezoelectric crystal to generate square-wave excitation pulses. The absence of wiring between driver and crystal provides excellent pulse control possibilities. It is shown that the power consumption varies with the excitation pulse width, which also affects the received ultrasound energy in a pulse echo system. To achieve maximum output ultrasound energy, an excitation pulse width of 100 ns= 0.44/f/sub osc,nom/ should be used. At a repetition rate of 1 kHz, the power consumption including losses in the driver stage varies from 96 /spl mu/W for an excitation pulse width of 240 ns, up to 126 /spl mu/W for an excitation pulse width of 130 ns. The performed SPICE simulations agree well with measured data.
This paper describes the design of a highly integrated ultrasound sensor where the piezoelectric ceramic transducer is used as the carrier for the driver electronics. Intended as one part in a complete portable, battery operated ultrasound sensor system, focus has been to achieve small size and low power consumption. An optimized ASIC driver stage is mounted directly on the piezoelectric transducer and connected using wire bond technology. The absence of wiring between driver and transducer provides excellent pulse control possibilities and eliminates the need for broad band matching networks. Estimates of the sensor power consumption are made based on the capacitive behavior of the piezoelectric transducer. System behavior and power consumption are simulated using SPICE models of the ultrasound transducer together with transistor level modelling of the driver stage. Measurements and simulations are presented of system power consumption and echo energy in a pulse echo setup. It is shown that the power consumption varies with the excitation pulse width, which also affects the received ultrasound energy in a pulse echo setup. The measured power consumption for a 16 mm diameter 4.4 MHz piezoelectric transducer varies between 95 μW and 130 μW at a repetition frequency of 1 kHz. As a lower repetition frequency gives a linearly lower power consumption, very long battery operating times can be achieved. The measured results come very close to simulations as well as estimated ideal minimum power consumption.
This paper describes the design of the complete transmit and receive electronics circuitry for a piezoelectric transducer in one single ASIC. The chip will be one building block in a thumb size battery operated ultrasound measurement system. The main design target has been to achieve extremely low power consumption while keeping the number of external components minimal. To overcome the dynamic range limitations imposed by a battery supply an on-chip boost converter uses one external inductor to generate up to 40 V for excitation of the transducer. The transducer itself is used as a storage capacitor, whereafter it is rapidly discharged to generate an ultrasound pulse. An on-chip amplifier with intermittent operation is controlled by a state machine and used to amplify incoming echoes. The chip has been fabricated in a 0.8 m high voltage CMOS process, with a total chip area of 12 mm2. Measurements verify the design approach. The power consumption for the system reaches within a factor of 2 of the power needed to charge the capacitance of the piezoelectric transducer from a fixed voltage source. The results show the possibility to achieve extremely low power consumption in a battery operated pulse–echo ultrasound measurement system.
Equivalent circuits for piezoelectric devices and ultrasonic transmission media can be used to cosimulate electronics and ultrasound parts in simulators originally intended for electronics. To achieve efficient systemlevel optimization, it is important to simulate correct, absolute amplitude of the ultrasound signal in the system, as this determines the requirements on the electronics regarding dynamic range, circuit noise, and power consumption.This paper presents methods to achieve correct, absolute amplitude of an ultrasound signal in a simulation of a pulse-echo system using equivalent circuits. This is achieved by taking into consideration loss due to diffraction and the effect of the cable that connects the electronics and the piezoelectric transducer. The conductive loss in the transmission line that models the propagation media of the ultrasound pulse is used to model the loss due to diffraction.Results show that the simulated amplitude of the echo follows measured values well in both near and far fields, with an offset of about 10%. The use of a coaxial cable introduces inductance and capacitance that affect the amplitude of a received echo. Amplitude variations of 60% were observed when the cable length was varied between 0.07 m and 2.3 m, with simulations predicting similar variations. The high precision in the achieved results show that electronic design and system optimization can rely on system simulations alone. This will simplify the development of integrated electronics aimed at ultrasound systems.
To address the growing field of on-line, out-of-hospital healthcare a front-end ADC for portable electrocardiographic systems has been designed. The converter is realized as a first-order, 3-bit ΣΔ with an oversampling ratio of 512. Performance is optimized to adhere to the standard IEC60601-2-47, which governs ambulatory ECG equipment. The single ended design achieves a dynamic range of 16 bits for signal offsets up to ±1.25 V. Measured power consumption is 60 μW with supplies of 2.6 V analog and 2.2 V digital.
In most comparator designs, a signal is preamplified before it is fed to the decision circuit which actually makes comparison. It is also desirable that the total comparator propagation delay, as well as its dispersion, is dominated by the delay and the dispersion of the preamplifier.This paper presents the analysis of the propagation delay in a multistage preamplifier and proposes a way to minimize the propagation delay dispersion by a non-even distribution of gain in the amplifier chain.
This paper presents a compensation structure to reduce the output common mode current of a rail-to-rail constant gm transconductance stage. The transconductance stage is a differential structure with the input transistors biased in weak inversion. This results in low power consumption and a simple relation between gm and tail currents. The constant gm is achieved by doubling the tail current in the active differential couple when the other one goes to cut off. Together with constant bias current in the output stage this can result in common mode bias current flowing from the output depending on the common mode input voltage. The proposed solution eliminates this problem by variation of the bias current in the output stage in relation to the tail currents in the differential couples. The transconductance stage was manufactured in a 0.35 um CMOS process. Measurement results are presented together with simulation data. The compensation structure cancels the common mode output currents for common mode input signals up to a frequency of 7 MHz.
This paper describes a design strategy towards a low power, DC level insensitive comparator with stable low power, level insensitive comparator with stable propagation time. The comparator b must suitable in applications were a constant propagation delay is critical, such as level crossing detection in ultrasound measurements and level crossing detection in ultrasound measurements and time quantization A/D convertem. The use of a long absolute propagation delay allows low power consumption while keeping the signal dependent propagation delay variation low. The comparator b able to process signals with all DC level within power rails due to a constant-gm, rail-to-rail, single-ended to differential converter implemented in the input stage. Schematic simulations show that the comparator has less than 1 ns delay variation at an absolute propagation delay of 12 ns. Test signals include frequencies from 0.5 MHz to 10 MHz, amplitudes fmm 30 mV to 1 V and all DC levels within rails.
A performance evaluation of a level-crossing analog-to-digital converter (ADC) is presented. It is shown that its signal-to-noise ratio (SNR) does not depend on the input-signal amplitude, which results in an almost-flat SNR for amplitudes that fall into the Nyquist criteria for irregular sampling. The influence of the reconstruction procedure on SNR is discussed, and possible limitations due to the comparator and clock on the performance of the ADC are analyzed. This analysis allows for specification of comparator and clock parameters such that they do not limit the ADC performance yet are not overestimated. In conclusion, a previously known level-crossing ADC design procedure is extended.
This paper presents the design of a continuous time voltage comparator with low propagation delay dispersion. The comparator is intended to be used as a building block for a level-crossing AD converter: a type of AD converter where the sampling moments are triggered when an input signal crosses predetermined threshold levels. This type of system sets very high demands on the time measurement and the comparator to achieve the desired performance. The comparator design is based on several techniques to minimize the comparator propagation delay dispersion. The comparator has been implemented in a 0.35 μm BiCMOS process. Measured results show good agreement with simulations. The slew rate related propagation delay dispersion is measured to 90 ps for an input frequency range from 3 to 10 MHz and amplitudes from 200 mV to 1.65 V. The comparator static power consumption is 9 mW.
Wireless Sensor Networks (WSNs) consist of small, autonomous devices with wireless networking capabilities. In order to further increase the applicability of WSNs in real world ap- plications, minimizing energy consumption and size are im- portant research topics. A WSN node itself is a complex system consisting of numerous components, and the energy consumption of the node depends heavily on the interac- tion between its components and their respective operation modes. To develop a power consumption model, we have investigated the power characteristics of a Bluetooth(BT)- equipped node based on COTS (commercial o®-the-shelf) components running standardized protocols for communica- tion. The characterization captures the transient behavior of the individual components as well as the dynamic behav- ior of the system as a whole. Although the parameters of the model are derived for a speci¯c node, the model and our conclusions can be applied to WSN nodes in general. Based on our model the estimated lifetime of a battery powered BT-equipped node can range from a couple of days to sev- eral months depending on battery and usage. This result indicates that COTS based sensor nodes can be used in a wide range of applications.
The use of PSpice models for piezoelectric devices and ultrasonic transmission media is of major importance in the design of electronics for ultrasonic systems. Today, these models include viscoelastic loss but disregard loss due to diffraction, i.e. beam spreading. This paper presents a method to include diffraction loss in PSpice simulations of ultrasonic systems. The conductive loss in the transmission line, that models the propagation media of the ultrasound pulse, is used to model the loss due to diffraction. Parameter variations for the piezoelectric device can affect the result greatly. Thus, a sensitivity analysis for the simulation model is presented. Measurements and simulations have been performed using a pulse echo system in water. Maximum distance to the reflector was 200 mm. The piezoelectric devices used were PZ-27 crystals with diameters 6 mm and 12 mm, with a center frequency of 4 MHz. Results show that the simulated amplitude of the echo follows measured values well in both near and far fields, with an offset of about 10%.
This paper presents electromagnetic simulations of a wireless power transfer system suitable for a monitoring system for detection of solder fatigue in power semiconductor modules. Power is provided wirelessly from a printed spiral coil on a printed circuit board to a silicon chip with an on-chip coil. We use and adapt a known gradient-ascent-based optimisation algorithm to obtain suitable coil geometries. For a frequency of 433 MHz, the simulations show an efficiency of -34.7 dB which we conclude is sufficient for the proposed monitoring system.
This paper analyses leakage current compensation techniques for low-power, bandgap temperature sensors. Experiments are conducted for circuits that compensate for collector-substrate, collector-base, body-drain and source-body leakage currents in a Brokaw bandgap sensor. The sensors are characterised and their failure modes are analysed at temperatures from 60 to 230∘C">230 ∘ C 230∘C . It is found that the most appropriate compensation circuit depends on the accuracy requirements of the application and on whether a stable reference voltage is required by other parts of the circuit. Experiments show that the power consumption is dominated by leakage current at high temperatures. One type of sensor was seen to consume 260 nW at 60∘C">60 ∘ C 60∘C , 2.1μW">2.1μW 2.1μW at 200∘C">200 ∘ C 200∘C and 14μW">14μW 14μW at 230∘C">230 ∘ C 230∘C . This work is motivated by the need to accurately monitor the temperature of power semiconductors in order to predict emerging faults in power semiconductor modules, a task for which cheap, single-chip, low-power, high-temperature, wireless bandgap temperature sensors are appropriate.
The design of a 450 nW bandgap temperature sensor in the 0 to 175 °C range is presented. The design demonstrates a leakage current compensation technique that is useful for low-power designs where transistor performance is limited. The technique mitigates the effects of leakage in Brokaw bandgap references by limiting the amount of excess current that is entering the bases of the main bipolar pair due to leakage. Using this technique, Monte Carlo simulations show an improvement factor of 7.6 for the variation of the temperature sensitivity over the full temperature range. For the variation of the reference voltage, Monte Carlo simulations show an improvement factor of 2.3.Sensors built using this technique can be used to accurately monitor the temperature of power semiconductors since wireless temperature sensors become feasible with sufficiently low power consumption.
This paper presents a theory for the power transfer efficiency to on-chip coils, with focus on load-dependence for low-power single-chip systems. The theory is verified with electromagnetic simulations modelled on a 350~nm process which in turn are verified by measurements on manufactured integrated circuits. The power transfer efficiency is evaluated by on-chip rectification of a 225~MHz signal transmitted by a spiral coil printed on a ceramic substrate at 10 mm of separation. Such an approach avoids the influence of off-chip parasitic elements such as bond-wires which would reduce the accuracy of the evaluation.It is found that there exists a lower limit for the load below which reducing the power consumption of on-chip circuits yield no increase in power consumption. The paper is focused on the analysis and verification of the theory behind this limit.We relate the results presented in this work to the application of wireless single-chip temperature monitoring of power semiconductors.
This paper presents a theory for the power transfer efficiency of printed circuit board coils to integrated circuit coils, with focus on load-dependence for low-power single-chip systems. The theory is verified with electromagnetic simulations modelled on a 350 nm CMOS process which in turn are verified by measurements on manufactured integrated circuits. The power transfer efficiency is evaluated by on-chip rectification of a 151 MHz signal transmitted by a spiral coil on a printed circuit board at 10 mm of separation to an on-chip coil. Such an approach avoids the influence of off-chip parasitic elements such as bond wires, which would reduce the accuracy of the evaluation.
It is found that there is a lower limit for the load below which reducing the power consumption of on-chip circuits yield no increase in voltage generated at the load. For the examined process technology, this limit appears to lie around 56 kΩ. The paper is focused on the analysis and verification of the theory behind this limit.
We relate the results presented in this work to the application of wireless single-chip temperature monitoring of power semiconductors and conclude that such a system would be compatible with this limit.