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  • 1.
    Acharya, Sarthak
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Delsing, Jerker
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    An Additive Production approach for Microvias and Multilayered polymer substrate patterning of 2.5μm feature sizes2020In: IEEE 70th Electronic Components and Technology Conference: ECTC 2020, IEEE, 2020, p. 1304-1308Conference paper (Other academic)
    Abstract [en]

    Consumer electronics market is escalating towards the miniaturization and the use of HDI-PCBs is dominating. Thus, the production technologies are adapting the Semi-Additive process (SAP) or modified-SAP (mSAP) methods over conventional subtractive print-and-etch methods. Most of the Smartphone manufacturers are using Substrate-like PCB (SLP) with mSAP techniques to scale down the Lines and Spaces (L&S) on PCBs equivalent to ICs. However, those processes still involve subtractive patterning in the intermediate stages of fabrication. In this paper, a fully additive multi-layer patterning process using an electroless copper plating has been investigated. This patterning process is based on modifying a polymer surface by activating a seed layer of grafting polymer chains on it using optimized UV-Laser parameters. This surface modification enables a strong bonding of Copper (Cu) onto the modified surface by Cu-plating. Using a micrometer via laser ablation and subsequent sub-micrometer laser lithography a 2.5D surface pattern has been achieved with the proposed technique.So far, using the proposed additive production process the feature sizes of 2.5 μm L&S and via of diameter 10 μm have been achieved.The via ablation and pattering were done by using 266nm and 375nm laser sources respectively.The substrates used are standard FR4 material and a layer of polyurethane of thickness 35μm coated on top of it. Analysis of the process parameters and their optimization has been done by factorial design method using Design Expert 12.0 software to show their contribution and significance in the production process.

  • 2.
    Acharya, Sarthak
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab. Department of Information Technology & Electrical Engineering, University of Oulu, 90570 Oulu, Finland.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Delsing, Jerker
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Fabrication Process for On-Board Geometries Using a Polymer Composite-Based Selective Metallization for Next-Generation Electronics Packaging2021In: Processes, ISSN 2227-9717, Vol. 9, no 9, article id 1634Article in journal (Refereed)
    Abstract [en]

    Advancements in production techniques in PCB manufacturing industries are still required as compared to silicon-ICs fabrications. One of the concerned areas in PCBs fabrication is the use of conventional methodologies for metallization. Most of the manufacturers are still using the traditional Copper (Cu) laminates on the base substrate and patterning the structures using lithography processes. As a result, significant amounts of metallic parts are etched away during any mass production process, causing unnecessary disposables leading to pollution. In this work, a new approach for Cu metallization is demonstrated with considerable step-reducing pattern-transfer mechanism. In the fabrication steps, a seed layer of covalent bonded metallization (CBM) chemistry on top of a dielectric epoxy resin is polymerized using actinic radiation intensity of a 375 nm UV laser source. The proposed method is capable of patterning any desirable geometries using the above-mentioned surface modification followed by metallization. To metallize the patterns, a proprietary electroless bath has been used. The metallic layer grows only on the selective polymer-activated locations and thus is called selective metallization. The highlight of this production technique is its occurrence at a low temperature (20–45 °C). In this paper, FR-4 as a base substrate and polyurethane (PU) as epoxy resin were used to achieve various geometries, useful in electronics packaging. In addition, analysis of the process parameters and some challenges witnessed during the process development are also outlined. As a use case, a planar inductor is fabricated to demonstrate the application of the proposed technique.

  • 3.
    Acharya, Sarthak
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Delsing, Jerker
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Realization of Embedded Passives using an additive Covalent bonded metallization approach2019In: 2019 22nd European Microelectronics and Packaging Conference & Exhibition (EMPC): Technical Papers, IEEE, 2019Conference paper (Other academic)
    Abstract [en]

    Miniaturization is the call of the day. Electronics shrinking and scaling technology is the priority of all manufacturers. PCBA Industry is working towards the elimination of solder joints, reduction in use of discrete and bulky components, lowering of assemble span, minimized latency etc. Embedded passive technology is playing a significant role in this roadmap by providing better signal performance, reduced parasitic and crosstalk. In this work, the primary focus is to develop a cost-efficient and flexible fabrication methodology that will be suitable for bulk production. A sequential build up (SBU) procedure is adopted with an additive lithography process to realize the passives with minimum possible feature size (<; 10 μm). A low cost insulating material, promising grafting solution and Laser assisted writing machine with optimized fabrication parameters are the highlights of this production method. A Computer Aided Design (CAD) software i.e. clewin is used during this process to pattern the mask for the entire process. Covalent bonded metallization (CBM) is the key process for the adhesion of copper layer on the desired site of the pattern. In the CBM process, a polymer surface is modified by grafting. The position of the surface modification is optically defined using a laser lithography system. Such surface modified samples are, then treated in an electroless copper process. Resulting in copper metallization only at the locations with a CBM modified surface. The verification of the copper deposition on the substrate is investigated using a high-resolution microscope followed by scanning electron microscopy (SEM). The confirmation of passive formation has been checked using kethley's source (electrical two-probe measurement). The first-order measured results showed the capacitance formed in the range of 0.3-8 pF. Further concrete measurements using standard methods are undergoing. One of the key advantage of this proposed process is its easiness and feasibility of at room temperature.

  • 4.
    Acharya, Sarthak
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Delsing, Jerker
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Scalability of Copper-Interconnects down to 3μm on Printed Boards by Laser-assisted-subtractive process2019In: Proceedings of: 2019 IMAPS Nordic Conference on Microelectronics Packaging (NordPac), IEEE, 2019, p. 206-209Conference paper (Refereed)
    Abstract [en]

    As per the latest roadmap of iNEMI, the global electronics market is emphasizing to identify disruptive technologies that can contribute towards denser, robust and tighter integration on the board level. Therefore, reduction in packaging factor of printed board can accommodate greater number of ICs to support miniaturization. This paper has shown an experimental method to pattern the metallic layer on a Printed circuit Board (PCB) to the smallest feature size. To investigate this, a commercially available FR-4 PCB with photosensitive material coat and a Copper (Cu) layer on it, is used. A reverse-mode Laser assisted writing is implemented to pattern the desired copper tracks. Soon after, a well-controlled development and chemical etching of the Laser-activated regions are done using Sodium Hydroxide solution followed by an aqueous solution of Sodium Persulfate. Current PCB interconnects used by the industries are of the order (~20 μm). Whereas the present work is a contribution towards achieving Copper interconnects with feature size 3.0μm. This miniaturization corresponds to 70% reduction in the feature size from 20 μm to 3μm. The natural adhesion of the Cu layer has remained intact even after the etching, shows the efficiency of the method adopted. Also, variation in the parameters such as etching time, etchant solution concentrations, temaperature, gain and exposure time of Laser beam and their corresponding effects are discussed. Other highlights of this subtractive method includes its cost-efficiency, lesser production time and repeatability.

  • 5.
    Acharya, Sarthak
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Sattar, Shahid
    Department of Physics & Electrical Engineering, Linnæus University, 39231 Kalmar, Sweden.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Delsing, Jerker
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Detailed Characterization of a Fully-Additive Covalent Bonded PCB Manufacturing Process (SBU-CBM Method)2022In: Processes, ISSN 2227-9717, Vol. 10, no 4, article id 636Article in journal (Refereed)
    Abstract [en]

    To bridge the technology gap between IC-level and board-level fabrications, a fully additive selective metallization has already been demonstrated in the literature. In this article, the surface characterization of each step involved in the fabrication process is outlined with bulk metallization of the surface. This production technique has used polyurethane as epoxy resin and proprietary grafting chemistry to functionalize the surface with covalent bonds on an FR-4 base substrate. The surface was then metalized using an electroless copper (Cu) bath. This sequential growth of layers on top of each other using an actinic laser beam and palladium (Pd) ions to deposit Cu is analyzed. State-of-the-art material characterization techniques were employed to investigate process mechanism at the interfaces. Density functional theory calculations were performed to validate the experimental evidence of covalent bonding of the layers. This manufacturing approach is capable of adding metallic layers in a selective manner to the printed circuit boards at considerably lower temperatures. A complete analysis of the process using bulk deposition of the materials is illustrated in this work.

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  • 6.
    Al-Maqdasi, Zainab
    et al.
    Luleå University of Technology, Department of Engineering Sciences and Mathematics, Material Science.
    Hajlane, Abdelghani
    Luleå University of Technology, Department of Engineering Sciences and Mathematics, Material Science. Materials Science and Nano-engineering, Mohammed VI Polytechnic University, Benguerir, Morocco.
    Renbi, Abdelghani
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Ouarga, Ayoub
    Materials Science and Nano-engineering, Mohammed VI Polytechnic University, Benguerir, Morocco.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Joffe, Roberts
    Luleå University of Technology, Department of Engineering Sciences and Mathematics, Material Science.
    Conductive Regenerated Cellulose Fibers by Electroless Plating2019In: Fibers, ISSN 2079-6439, Vol. 7, no 5, article id 38Article in journal (Refereed)
    Abstract [en]

    Continuous metallized regenerated cellulose fibers for advanced applications (e.g. multi-functional composites) are produced by electroless copper plating. Copper is successfully deposited on the surface of cellulose fibers using commercial cyanide-free electroless copper plating package commonly available for manufacturing of printed wiring boards. The deposited copper is found to enhance the thermal stability, electrical conductivity and resistance to moisture uptake of the fibers. On the other hand, involved chemistry results in altering the molecular structure of the fibers as is indicated by the degradation of their mechanical performance (tensile strength and modulus).

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    fulltext
  • 7.
    Al-Maqdasi, Zainab
    et al.
    Luleå University of Technology, Department of Engineering Sciences and Mathematics, Material Science.
    Joffe, Roberts
    Luleå University of Technology, Department of Engineering Sciences and Mathematics, Material Science.
    Ouarga, Ayoub
    High Throughput Multidisciplinary Research Laboratory, Mohammed VI Polytechnic University (UM6P), Lot 660—Hay Moulay Rachid, 43150 Benguerir, Morocco.
    Emami, Nazanin
    Luleå University of Technology, Department of Engineering Sciences and Mathematics, Machine Elements.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Landström, Anton
    Luleå University of Technology, Department of Engineering Sciences and Mathematics, Material Science.
    Hajlane, Abdelghani
    Laboratory of Crystallography and Materials Sciences, National Graduate School of Engineering of Caen, 6 Boulevard Maréchal Juin, 14000 Caen, France.
    Conductive Regenerated Cellulose Fibers for Multi-Functional Composites: Mechanical and Structural Investigation2021In: Materials, ISSN 1996-1944, E-ISSN 1996-1944, Vol. 14, no 7, article id 1746Article in journal (Refereed)
    Abstract [en]

    Regenerated cellulose fibers coated with copper via electroless plating process are investigated for their mechanical properties, molecular structure changes, and suitability for use in sensing applications. Mechanical properties are evaluated in terms of tensile stiffness and strength of fiber tows before, during and after the plating process. The effect of the treatment on the molecular structure of fibers is investigated by measuring their thermal stability with differential scanning calorimetry and obtaining Raman spectra of fibers at different stages of the treatment. Results show that the last stage in the electroless process (the plating step) is the most detrimental, causing changes in fibers’ properties. Fibers seem to lose their structural integrity and develop surface defects that result in a substantial loss in their mechanical strength. However, repeating the process more than once or elongating the residence time in the plating bath does not show a further negative effect on the strength but contributes to the increase in the copper coating thickness, and, subsequently, the final stiffness of the tows. Monitoring the changes in resistance values with applied strain on a model composite made of these conductive tows show an excellent correlation between the increase in strain and increase in electrical resistance. These results indicate that these fibers show potential when combined with conventional composites of glass or carbon fibers as structure monitoring devices without largely affecting their mechanical performance.

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  • 8.
    Aziz, Abdullah
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Schelén, Olov
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Bodin, Ulf
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Distributed Digital Twins as Proxies-Unlocking Composability & Flexibility for Purpose-Oriented Digital Twins2023In: IEEE Access, E-ISSN 2169-3536, Vol. 11, p. 137577-137593Article in journal (Refereed)
    Abstract [en]

    In the realm of Industrial Internet of Things (IoT) and Industrial Cyber-Physical Systems (ICPS), Digital Twins (DTs) have revolutionized the management of physical entities. However, existing implementations often face constraints due to hardware-centric approaches and limited flexibility. This article introduces a transformative paradigm that harnesses the potential of distributed Digital Twins as proxies, enabling software-centricity and unlocking composability and flexibility for purpose-oriented digital twin development and deployment. The proposed microservices-based architecture, rooted in service-oriented architecture (SOA) and microservices principles, emphasizes reusability, modularity, and scalability. Leveraging the Lean Digital Twin Methodology and packaged business capabilities expedites digital twin creation and deployment, facilitating dynamic responses to evolving industrial demands. This architecture segments the industrial realm into physical and virtual spaces, where core components are responsible for digital twin management, deployment, and secure interactions. By abstracting and virtualizing physical entities into individual digital twins, this approach establishes the groundwork for purpose-oriented composite digital twin creation. Our key contributions involve a comprehensive exposition of the architecture, a practical proof-of-concept (PoC) implementation, and the application of the architecture in a use-case scenario. Additionally, we provide an analysis, including a quantitative evaluation of the proxy aspect and a qualitative comparison with traditional approaches. This assessment emphasizes key properties such as reusability, modularity, abstraction, discoverability, and security, transcending the limitations of contemporary industrial systems and enabling agile, adaptable digital proxies to meet modern industrial demands.

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  • 9.
    Bhoi, Bandan Kumar
    et al.
    Department of Electronics and Telecommunication, Veer Surendra Sai, University of Technology, Burla, India.
    Misa, Neeraj Kumar
    Department of Electronics and Communication Engineering, Bharat Institute of Engineering and Technology, Hyderabad, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Acharya, Sarthak
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Analyzing Design Parameters of Nano-Magnetic Technology Based Converter Circuit2019In: VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Revised Selected Papers / [ed] Dr. Anirban Sengupta, Dr. Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma, Springer, 2019, p. 34-46Conference paper (Refereed)
    Abstract [en]

    Digital circuits need improvement in computation speed, reducing circuit complexity and power consumption. Emerging Technology NML can be such an architecture at nano-scale and thus emerges as a viable alternative for the digital CMOS VLSI. This technology has the capability to compute the logic as well as storage into the same device, which points out that it great potential for emerging technology. Since Nano-magnetic, technology fast approaches its minimal feature size, high device density and operate at room temperature. NML based circuits synthesis has to opt for novel half subtraction and Binary-to-Gray architecture for achieving minimal complexity and high-speed performance. This manuscript pro-poses area efficient binary half-subtraction and Binary-to-Gray converter architecture. Circuits’ synthesize are performed by MagCAD tool and simulate by Modelsim simulator. The circuit’s performance are estimated over other existing designs. The proposed converter consume 73.73%, and 94.49% less area than the converter designed using QCA and CMOS technique respectively. This is a significant contribution to this paper. Simulation results of converter show that the critical path delay falls within 0.15 µs.

  • 10.
    Chouhan, Shailesh
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Halonen, Kari
    Department of Micro and Nano Sciences, School of Electrical Engineering, Aalto University.
    A 352nW, 30 ppm/°C all MOS nano ampere current reference circuit2017In: Microelectronics Journal, ISSN 0959-8324, Vol. 69, p. 45-52Article in journal (Refereed)
    Abstract [en]

    In this work, an ultra low power all-MOSFET based current reference circuit, developed in 0.18 µm CMOS technology, is presented. The proposed circuit is based on the classical resistor-less beta multiplier circuit with an additional temperature compensation feature. The circuit is capable of providing the reference current in a nanoampere range for the supply voltage ranging from 1 V to 2 V in the industrial temperature range of −40 °C to 85 °C. The measurements were performed on 10 prototypes. The measured mean value of the reference current is 58.7 nA with a mean temperature coefficient value of 30 ppm/°C. In addition, the measured mean line regulation is 3.4%/V in the given supply voltage range. The total current consumption of the circuit is 352 nA and the chip area is 0.036 mm2.

  • 11.
    Chouhan, Shailesh Sing
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Halonen, Kari
    Department of Micro-and Nanosciences, School of Electrical Engineering, Aalto University .
    Ultra low power beta multiplier-based current reference circuit2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 93, no 3, p. 523-529Article in journal (Refereed)
    Abstract [en]

     This work presents a current reference circuit fabricated in a standard 0.18 μm CMOS technology. The reference current is obtained by applying thermal compensation voltage in the conventional self-biased or beta multiplier-based current reference circuit. Eight prototypes of the proposed architecture were measured which have resulted into the mean reference current of 26.1 nA with the temperature coefficient of 202.1 ppm/°C. These measurements were performed in the temperature range of − 40 to + 85 °C. The circuit is capable of working over the supply voltage range of 1–2 V with the measured mean line sensitivity of 2.18%/V. The maximum measured power dissipation of the circuit is 104 nW at 2 V.

  • 12.
    Chouhan, Shailesh Singh
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Halonen, Kari
    Department of Electronics and Nanoengineering, Aalto University, Espoo, Finland.
    A 40 nW CMOS-Based Temperature Sensor with Calibration Free Inaccuracy within ±0.6 ◦C2019In: Electronics, E-ISSN 2079-9292, Vol. 8, no 11, article id 1275Article in journal (Refereed)
    Abstract [en]

    In this study, a temperature equivalent voltage signal was obtained by subtracting output voltages received from two individual temperature sensors. These sensors work in the subthreshold region and generate the output voltage signals that are proportional and complementary to the temperature. Over the temperature range of −40 &#x2218;" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C to +85 &#x2218;" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C without using any calibration method, absolute temperature inaccuracy less than ±0.6 &#x2218;" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C was attained from the measurement of five prototypes of the proposed temperature sensor. The implementation was done in a standard 0.18 &#x3BC;" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">μ m CMOS technology with a total area of 0.0018 mm 2" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">2. The total power consumption is 40 nW for a supply voltage of 1.2 V measured at room temperature.

  • 13.
    Imani, Roghayeh
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Chouhan, Shailesh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Putaala, Jussi
    Microelectronics Research Unit, University of Oulu, Oulu, Finland.
    Nousiainen, Olli
    Materials and Mechanical Engineering Research Unit, University of Oulu, Oulu, Finland.
    Hagberg, Juha
    Microelectronics Research Unit, University of Oulu, Oulu, Finland.
    Myllymäki, Sami
    Microelectronics Research Unit, University of Oulu, Oulu, Finland.
    Acharya, Sarthak
    Department of Information Technology and Electrical Engineering, University of Oulu, Oulu, Finland.
    Jantunen, Heli
    Microelectronics Research Unit, University of Oulu, Oulu, Finland.
    Delsing, Jerker
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    A Fully Additive Fabrication Approach for sub-10-Micrometer Microvia Suitable for 3-D System-in-Package Integration2023In: Proceedings - IEEE 73rd Electronic Components and Technology Conference, ECTC 2023, Institute of Electrical and Electronics Engineers Inc. , 2023, p. 1926-1931Conference paper (Refereed)
    Abstract [en]

    The semiconductor industry demands high input/output (I/O) density, requiring sub-l0-micrometer microvia. Here we propose a novel, fully additive, economical approach for creating and copper plating of microvias. The experimental process consisted of three stages. In Stage I, a polyurethane layer was spin-coated onto a FR-4 PCB base, followed by target copper layer deposition using the sequential build-up-covalent bonded metallization (SBU -CBM) method. In Stage II, first another layer of polyurethane was spin-coated on the top of the target copper layer, and then a microvia was created on the polyurethane layer using a picosecond pulsed ultraviolet (UV) laser. Finally, in Stage III, the SBU-CBM method was used to selectively copper plating of the microvia. Optical microscopy and cross-section scanning electron microscopy (SEM) images confirmed the successful formation and copper plating of sub-l0 micrometer microvia.

  • 14.
    Imani, Roghayeh
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Delsing, Jerker
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Acharya, Sarthak
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab. M3S Research group, Department of Information, Technology and Electrical Engineering, University of Oulu, Oulu, Finland.
    A Fully Additive Approach for the Fabrication of Split-Ring Resonator Metasurfaces2022In: Proceedings: IEEE 72nd Electronic Components and Technology Conference (ECTC 2022), IEEE, 2022, p. 1834-1840Conference paper (Other academic)
    Abstract [en]

    Metasurfaces, as a two-dimensional (2D) form of metamaterial, offer the possibility of designing miniaturized antennas for radio frequency (RF) energy harvesting systems with high efficiency, but fabrication of these antennas is still a major challenge. Printed circuit board (PCB) lithography, utilizing subtractive etch-and-print techniques to create metal interconnects on PCBs, was the first technique used to create metasurfaces antennas and remains the dominant technique to this day. The development of large-area fabrication techniques that are flexible, precise, uniform, cost-effective, and environmentally friendly is urgently needed for creating next-generation metasurfaces antenna. The present study reports a new fully additive manufacturing method for the fabrication of copper split-ring resonator (SRR) arrays on a PCB as a planar compact metasurfaces antenna. This new method was developed by combining sequential build up (SBU), laser direct writing (LDW), and covalent bonded metallization (CBM) methods and called (SBU-CBM). In this method, standard FR-4 covered with a layer of polyurethane was used as a basic PCB. The polymer surface was coated with a grafting molecule, followed by LDW to pattern the SRR array on the PCB. Finally, in electroless plating, only the laser-scanned area was selectively plated, and copper covalent bond metallization was selectively plated on the SRR pattern. Copper SRR arrays with different sizes were successfully fabricated on PCB using the SBU-CBM method. Copper strip lines within the SRR repeating building block were miniaturized up to 5 μm. To the best of our knowledge, this is the smallest size of a PCB antenna that has been reported to date.

  • 15.
    Khan, Sajid
    et al.
    Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, India.
    Gupta, Neha
    Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, India.
    Vishvakarma, Abhinav
    Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Pandey, Jai Gopal
    Integrated Systems Group, CSIR- Central Electronics Engineering Research Institute (CEERI)Pilani, India.
    Vishvakarma, Santosh Kumar
    Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, India.
    Dual-Edge Triggered Lightweight Implementation of AES for IoT Security2019In: VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Revised Selected Papers / [ed] Sengupta A., Dasgupta S., Singh V., Sharma R., Kumar Vishvakarma S., Springer, 2019, p. 298-307Conference paper (Refereed)
    Abstract [en]

    Internet of Things (IoT) is now a growing part of our life. More than 10 billion devices are already connected, and more are expected to be deployed in the next coming years. To provide a practical solution for security, privacy and trust is the main concern for deploying IoT in such a large scale. For security and privacy in IoT, cryptography is the required solutions. AES algorithm is a well known, highly secure and symmetric key algorithm, but the area and power budget of AES makes it unsuitable for IoT Security. In this paper, we have presented a lightweight implementation of AES, with dual-edge triggered S-box. The proposed architecture has been implemented on FPGA as well as in ASIC on 180 nm technology. The proposed architecture uses a 32-bit data path to encrypt 128-bit plain-text with 128-bit cipher-key. ASIC implementation of the proposed architecture results in low-power (122.7 &#x03BC;" role="presentation" style="box-sizing: border-box; display: inline-table; line-height: normal; letter-spacing: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; max-height: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">μμW at 1 V) consumption with a reduction in the hardware overhead by 30% and a throughput of 23 Mbps at 10 MHz clock frequency.

  • 16.
    Khan, Sajid
    et al.
    Nanoscale Devices, VLSI Circuit & System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, M.P. 453552, India.
    Prasad Shah, Ambika
    Discipline of Electrical Engineering, Indian Institute of Technology Jammu, J&K 181221, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Pandey, Jai Gopal
    Integrated System Laboratory, CSIR-CEERI, Pilani 333031, Rajasthan, India.
    Vishvakarma, Santosh Kumar
    Nanoscale Devices, VLSI Circuit & System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, M.P. 453552, India.
    D flip-flop based TRNG with zero hardware cost for IoT security applications2021In: Microelectronics and reliability, ISSN 0026-2714, E-ISSN 1872-941X, Vol. 120, article id 114098Article in journal (Refereed)
    Abstract [en]

    System-on-chips (SoCs) for the Internet of things (IoT) applications require hardware-based integrated random number generators for the secure transmission of information. However, they have limited hardware and power budget, which limits the use of on-chip dedicated True Random Number Generator (TRNG). In this work, a symmetric D flip-flop with integrated TRNG is proposed. The proposed architecture is implemented using a standard 40 nm CMOS technology. The post-layout simulation results show that it offers good randomness with low energy-per-bit. In addition, the circuit has passed all the tests of NIST without any post-processing. When compared with the conventional D flip-flop, it has almost negligible area overhead that is only 0.14%. An FPGA implementation is also presented as a proof of concept that confirms the simulation results. Advanced Encryption Standard (AES) key expansion algorithm is also implemented to demonstrate the dual usage of the proposed D flip-flop.

  • 17.
    Khan, Sajid
    et al.
    Nanoscale Devices, VLSI Circuit & System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore.
    Shah, Ambika Prasad
    Institute for Microelectronics, Technische Universität Wien.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Gupta, Neha
    Nanoscale Devices, VLSI Circuit & System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore.
    Pandey, Jai Gopal
    Integrated System Group, CSIR-CEERI.
    Vishvakarma, Santosh Kumar
    Nanoscale Devices, VLSI Circuit & System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore.
    A symmetric D flip-flop based PUF with improved uniqueness2020In: Microelectronics and reliability, ISSN 0026-2714, E-ISSN 1872-941X, Vol. 106, article id 113595Article in journal (Refereed)
    Abstract [en]

    Physically unclonable functions (PUF) emerged as security primitives that generate high entropy, temper resilient bits for security applications. However, the implementation area budget limits their use in lightweight applications such as IoT, RFID, and biomedical applications. In the form of SRAM or D flip-flop, intrinsic PUFs are abundantly available in almost all of the designs. Being an integral part of the design, they can be used with compromised performance. In this work, to address the usage of intrinsic PUF, a D flip-flop based lightweight PUF is proposed. The proposed architecture is implemented on 40 nm CMOS technology. The simulation results show that it offers a uniqueness of 0.502 and the worst-case reliability of 95.89% at high temperature 125 °C and 97.89% at a supply voltage of 1.2 V. To evaluate the performance of various PUF architectures, A novel term, the uniqueness-to-reliability ratio, is proposed. When compared to the conventional D flip-flop, it offers 4.491 times more uniqueness and 127.74 times more uniqueness-to-reliability ratio with the same layout area. Since it uses the symmetrical structure, unlike other architectures, the proposed architecture does not require any post-processing schemes for bias removal, which further saves the silicon area. To verify the functional correctness of the simulation results, an FPGA implementation of the conventional and proposed D Flip-flop is also presented.

  • 18.
    Khan, Sajid
    et al.
    Indian Institute of Technology Indore, Indore, India.
    Shah, Ambika Prasad
    Institute for Microelectronics, Technische Universität Wien, Vienna, Austria.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Rani, Sudha
    Indian Institute of Technology Indore, Indore, India.
    Gupta, Neha
    Indian Institute of Technology Indore, Indore, India.
    Pandey, Jai Gopal
    Integrated System Group, CSIR-CEERI, Pilani, Rajasthan, India.
    Vishvakarma, Santosh Kumar
    Indian Institute of Technology Indore, Indore, India.
    Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications2020In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 103, no 3, p. 477-492Article in journal (Refereed)
    Abstract [en]

    Physically unclonable functions (PUF) are digital fingerprints which generate high entropy, temper-resilient keys and/or chip-identifiers for security applications. When considering the miniaturized hardware development for the Internet of Things (IoT), security is of high importance. In this case, PUF designing using SRAM or D flip-flops are quite common but with compromised uniqueness due to the limited silicon area. In this work, a symmetric tri-state D flip-flop based lightweight PUF is proposed with increased uniqueness. The proposed architecture is implemented using a standard 40 nm CMOS technology. The post-layout simulation results show that it offers a uniqueness of 0.4994, which is the highest among all the considered architectures. Compared to the Arbiter PUF the proposed architecture has 0.267 , 0.064 , and 0.043 less, power, silicon area, and energy per bit, respectively. Similarly, when compared with the Ring Oscillator PUF, the proposed architecture has 0.017 , 0.031 , and 0.0005 less, power, silicon area, and energy per bit, respectively. Also, unlike other flip-flop based PUF, the proposed one does not require any post-processing block to remove the bias, thus contributes to saving the total implementation area and power of the system. An FPGA implementation is also presented as a proof-of-concept to verify functional correctness. For a better performance comparison among the considered architectures, a novel figure of merit (FOM) considering power, reliability, delay, silicon area, and uniqueness has been proposed, and it is observed that the proposed architecture offers the highest FOM among considered PUF architectures.

  • 19.
    Khan, Sajid
    et al.
    Nanoscale Devices, VLSI Circuit & System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, India.
    Shah, Ambika Prasad
    Institute for Microelectronics, Technische Universität Wien, Vienna, Austria.
    Gupta, Neha
    Nanoscale Devices, VLSI Circuit & System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Pandey, Jai Gopal
    Integrated System Group, CSIR-CEERI, Pilani, Rajasthan, India.
    Vishvakarma, Santosh Kumar
    Nanoscale Devices, VLSI Circuit & System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, India.
    An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications2019In: Microelectronics Journal, ISSN 0959-8324, Vol. 92, article id 104605Article in journal (Refereed)
    Abstract [en]

    Physically Unclonable Functions (PUF) have emerged as security primitives which can generate high entropy, temper resilient bits for security applications. However, the power budget of the ring oscillator (RO) PUF limits the use of RO PUF in IoT applications, in this concern a low power variant of RO PUF is much needed. In this paper, we have presented an ultra-low power, lightweight, configurable RO PUF based on the 4T XOR architecture. The proposed architecture is aging resilient; hence it produces a stable PUF output over the years. Also, it has a large number of challenge-response-pair (CRP) compared to the other architectures, which makes it suitable for chip identification as well as cryptographic key generation. The proposed PUF is implemented on 40 nm CMOS technology, and for the validation of design, we have also implemented on FPGA. The simulation results show that it has a uniqueness of 0.489 and worst-case reliability of 96.43% and 93.15% at 125 °C and 1.2 V, respectively. Compared to the conventional RO PUF it consumes 98.06% and 95.47% less dynamic and leakage power, respectively.

  • 20.
    Panchal, Vaidik
    et al.
    IET-Devi Ahilya University, Indore, MP, India.
    Sankla, Himanshu
    IET-Devi Ahilya University, Indore, MP, India.
    Sharma, Priyanka
    IET-Devi Ahilya University, Indore, MP, India.
    Neema, Vaibhav
    E&TC Engineering Department, IET-Devi Ahilya University, Indore, MP, India.
    Panchal, Ashish
    E&TC Engineering Department, IET-Devi Ahilya University, Indore, MP, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    FPGA implementation of proposed number plate localization algorithm based on YOLOv2 (You Only Look Once)2023In: Microsystem Technologies: Micro- and Nanosystems Information Storage and Processing Systems, ISSN 0946-7076, E-ISSN 1432-1858, Vol. 29, no 10, p. 1501-1513Article in journal (Refereed)
    Abstract [en]

    Many algorithms used in machine learning and artificial intelligence rely on exact object identification and recognition as their foundation for efficiency and accuracy. Hardware implementation of such methods, when implemented, serves to boost the reliability and productivity of object detection in a wide range of contexts. Hardware implementation of such an algorithm takes a lot of resources and a huge amount of calculation time. The object detection and recognition process require a collection of complex algorithms and a series of filtering approaches to work beyond the boundary conditions. The YOLOv2 network is superior to filters and complicated algorithms for this problem. The authors of this study propose an enhanced YOLOv2 Network for object recognition and a novel approach for optimising the existing YOLOv2 Network for localization to pinpoint the ROI that can be used to scale down and contain the object&apos;s original area. The network is proposed by configuring the existing YOLOv2 with additional convolution layers and dropout layers. The dropout layers are added to reduce the dependency on a single neuron and is an effective way of preventing overfitting of the network. Also, instead of ReLU as the activation function, we are using the Swish activation function which tends to provide better results. By isolating and producing the region of interest (ROI) from the original image, the algorithm was able to significantly cut down on both the number of resources needed and the time needed to complete the task. The proposed work is implemented on an FPGA board (Xilinx Zynq-Z7010 FPGA board), and the dataset is collected and prepared by the authors. Data augmentation is done to enhance the training data to enhance the training data, which results in better trained network. MATLAB is used to demonstrate the feasibility of the work and provide a thorough evaluation of its merits. The results show that the accuracy of the conventional algorithm approach drops to 20–30% once you move outside the boundaries, whereas the accuracy of the proposed work increases to 60–70% and a 15–20% increase in efficiency with proposed network based on YOLOv2. The proposed algorithm is three times as fast as the standard method while using only 35 percent as much technology.

  • 21.
    Sharma, Priyanka
    et al.
    Department of Electronics and Telecommunication, IET-Devi Ahilya University, Indore, India.
    Neema, Vaibhav
    Department of Electronics and Telecommunication, IET-Devi Ahilya University, Indore, India.
    Vishvakarma, Santosh Kumar
    Electrical Engineering Department, Indian Institute of Technology Indore, Indore, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    MPEG/H256 video encoder with 6T/8T hybrid memory architecture for high quality output at lower supply2023In: Memories - Materials, Devices, Circuits and Systems, ISSN 2773-0646, Vol. 4, article id 100028Article in journal (Refereed)
    Abstract [en]

    The use of Multimedia video content is increased rapidly in the past decade, and most multimedia video content is used by mobile phone users. Multimedia video processing consumes significant power during video compression, and thus low power multimedia video compression is essential for battery operated devices. Moving Picture Experts Group (MPEG) Video encoding is giving a higher compression rate and low bandwidth requirement. Conventional MPEG Video encoding architecture uses the conventional 6T memory cells to store video frames for further compression processing. The failure probability of 6T cells is significantly large (0.0988 at 600 mV supply voltage), leading to a decrease in the output quality of the encoded video. From the hybrid memory matrix formulation, it is calculated that storing higher-order MSB bits in highly stable memory cells will provide high-quality video encoding processing as compared to the conventional technique because the human eye is more susceptible to higher-order luminance bits. Hence, in this research work instant of using conventional 6T memory cells during video encoding processing, a unique Hybrid 6T/8T memory architecture is proposed, where the 8-bit Luminance pixels are stored favourably in consonance with their effect on the output quality. The higher order luminance bits (MSB’s) require high stability and thus these bits are stored in the 8T bit cells and the remaining bits (LSB’s) are stored in the conventional 6T bit cells for high-quality video encoding processing. This research article also proposes a separate memory peripheral circuitry for hybrid memory architecture for video encoding techniques. In addition, this article proposes a unique architecture for parallel video processing with the use of a hybrid pixel memory array. The failure probability of 6T and 8T at the worst failure corner (FS corner for read and SF corner for write) is simulated for 30000 Monte-Carlo simulations points at 45 nm CMOS technology node using CADENCE EDA tool. For the simulation work here, a standard Common Intermediate Format/Quarter Common Intermediate Format (CIF/QCIF) Coastguard video sample is used and for output quality here average PSNR method is used and simulation work is performed using the MATLAB tool.

    The worst PSNR for conventional 6T memory array and Hybrid memory array at 600 mV supply voltage shows improvement in worst minimum PSNR as 6.43 dB is calculated. 30% less power consumption to conventional memory architecture.

    Download full text (pdf)
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  • 22.
    Sharma, V.
    et al.
    Nanoscale Devices, VLSI Circuit & System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, India.
    Vishvakarma, S.
    Nanoscale Devices, VLSI Circuit & System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Halonen, K.
    Electronic Circuit Design Lab, Department of Electronics and Nano Engineering, Aalto University, Espoo, Finland.
    A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes2018In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 46, no 12, p. 2314-2333Article in journal (Refereed)
    Abstract [en]

    In this work, a data-dependent feedback-cutting–based bit-interleaved 12T static random access memory (SRAM) cell is proposed, which enhances the write margin in terms of write trip point (WTP) and write static noise margin (WSNM) by 2.14× and 8.99× whereas read stability in terms of dynamic read noise margin (DRNM) and read static noise margin (RSNM) by 1.06× and 2.6 ×, respectively, for 0.4 V when compared with a conventional 6T SRAM cell. The standby power has also been reduced to 0.93× with an area overhead of 1.49× as that of 6T. Monte Carlo simulation results show that the proposed cell offers a robust write margin when compared with the state-of-the-art memory cells available in the literature. An analytical model of WSNM for 12T operating in subthreshold region is also proposed, which has been verified using the simulation results. Finally, a small SRAM macro along with its independent memory controller has been designed. 

  • 23.
    Sharma, Vishal
    et al.
    Nanoscale Devices, VLSI Circuit and System Design Lab, Electrical Engineering, Indian Institute of Technology Indore, Indore, India.
    Bisht, Pranshu
    Nanoscale Devices, VLSI Circuit and System Design Lab, Electrical Engineering, Indian Institute of Technology Indore, Indore, India.
    Dalal, Abhishek
    Nanoscale Devices, VLSI Circuit and System Design Lab, Electrical Engineering, Indian Institute of Technology Indore, Indore, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Jattana, H. S.
    SCL Mohali, Department of Space, Govt. of India, Ajitgarh, India.
    Vishvakarma, Santosh Kumar
    Nanoscale Devices, VLSI Circuit and System Design Lab, Electrical Engineering, Indian Institute of Technology Indore, Indore, India.
    A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design2019In: VLSI Design and Test: 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers / [ed] S. Rajaram; N.B. Balamurugan; D. Gracia Nirmala Rani; Virendra Singh, Springer, 2019, p. 551-564Conference paper (Refereed)
    Abstract [en]

    This work presents a new bit-interleaving low-power 11T subthreshold SRAM cell with the Data-Dependent Partial-Feedback Cutting to improve the write ability. The isolated read path of 11T enhances the read static noise margin (RSNM) which is equivalent to that of its hold SNM (HSNM), while the incorporated PMOS stacking in each of the inverter helps to reduce the leakage power of the cell. The half-select free behavior of the proposed 11T cell facilitates the bit-interleaving architecture of memory array that reduces the multi-bits error occurrence in a single word of data, and thus enhance the soft error tolerance. Using the proposed cell, a four-input FPGA lookup table (LUT) has been implemented working on 0.4V supply, which consumes 0.59× less leakage power as compared to that of 6T LUT. Finally, a two adjacent bits error correction technique is also suggested to incorporate with the proposed bit-interleaving 11T array, so that the effect of soft error can almost be neglected. It consumes comparable leakage and read access energy to that of one-bit error correcting conventional hamming code.

  • 24.
    Sharma, Vishal
    et al.
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, India.
    Bisht, Pranshu
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, India.
    Dalal, Abhishek
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, India.
    Gopal, Maisagalla
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, India.
    Vishvakarma, Santosh Kumar
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications2019In: AEU - International Journal of Electronics and Communications, ISSN 1434-8411, E-ISSN 1618-0399, Vol. 104, no May, p. 10-22Article in journal (Refereed)
    Abstract [en]

    This work presents a half-select free 12T SRAM cell with Data-Dependent Feedback Cutting approach to improve the write ability and isolated read path to enhance the read stability. The enhanced read and write ability is 1.95&#xD7;" role="presentation"> and 2.84&#xD7;" role="presentation"> larger respectively than that of the conventional 6T cell at 0.4 V. The half-select free behavior of proposed cell using the cross-point read/write structure facilitates the bit-interleaving memory architecture to effectively reduce the multi-bits soft error occurrence. The incorporated PMOS stacking effect in inverter pairs of the proposed cell offers the reduced leakage power which is 0.59&#xD7;" role="presentation"> to that of 6T, at 0.4 V supply. To further minimize the leakage power at array level, the bit lines between two adjacent cells have been shared that consumes only 0.38&#xD7;" role="presentation"> leakage power than that of the conventional 6T array for a 1 KB macro. Moreover, a Reconfigurable FPGA architecture is proposed for low power applications. The simulated static and active power consumption of 12T SRAM based reconfigurable FPGA is 0.22&#xD7;" role="presentation"> and 0.45&#xD7;" role="presentation"> when compared with the regular 12T FPGA. Finally, a Double Adjacent-bits Error Detection and Correction (DAEDC) scheme is suggested for the proposed bit-interleaved 12T SRAM array, to reduce the soft error effects.

  • 25.
    Sharma, Vishal
    et al.
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore .
    Gopal, Maisagalla
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore .
    Singh, Pooran
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore .
    Vishvakarma1, Santosh Kumar
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore .
    Chouhan, Shailesh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications2019In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 98, no 2, p. 331-346Article in journal (Refereed)
    Abstract [en]

    With the increased requirement of on-chip data computations in internet of things based applications, the embedded on-chip SRAM memory has been under its renovation stage to overcome the classical problems like stability and poor energy efficiency. In this work, a data-dependent-power-supply mechanism for a new 11T SRAM cell is proposed with ultra-low leakage and improved read/write stability against the process–voltage–temperature variations. The proposed cell consumes static power in the fraction of picowatt range and has considerable enhancement in the value of write static noise margin (WSNM). In addition, the use of associated read decoupling approach, with the column-based read buffer, further improves the read stability of the proposed cell and make it comparable with the hold stability value. The percentage reduction in the leakage power of proposed 11T cell is 99.97&#x0025;">99.97% 99.97% , 99.93&#x0025;">99.93% 99.93% and 99.97&#x0025;">99.97% 99.97% , while the WSNM 1 is 6.98&#x00D7;">6.98× 6.98× , 3.12&#x00D7;">3.12× 3.12× and 1.46&#x00D7;">1.46× 1.46× , and WSNM 0 is 5.55&#x00D7;">5.55× 5.55× , 1.25&#x00D7;">1.25× 1.25× and 1.16&#x00D7;">1.16× 1.16× larger when operating at 0.4 V and compared to the conventional 6T and threshold voltage techniques based VTH_9T and data aware write assist (DAWA) 12T SRAM cell structures respectively. Iread/Ileak">I read /I leak  Iread/Ileak ratio for the proposed cell has improved by 6.55&#x00D7;">6.55× 6.55× , 6.22&#x00D7;">6.22× 6.22× and 5.11&#x00D7;">5.11× 5.11× when compared with the 6T, VTH_9T and DAWA12T SRAM to increase the memory density. Further, the post-layout Monte Carlo simulation results (2000 samples) confirm the robustness of the proposed cell against the process variations.

  • 26.
    Sharma, Vishal
    et al.
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology Indore, Indore, M.P., 453552, India.
    Gupta, Neha
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology Indore, Indore, M.P., 453552, India.
    Shah, Ambika Prasad
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology Indore, Indore, M.P., 453552, India.
    Vishvakarma, Santosh Kumar
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology Indore, Indore, M.P., 453552, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes2021In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 107, no 2, p. 339-352Article in journal (Refereed)
    Abstract [en]

    The work proposes an 11T SRAM cell which confirms its reliability for Internet of Things (IoT) based health monitoring system. The cell executes improved write and read ability using data-dependent feedback cutting and read decoupled access path mechanism respectively. The write and read stabilities of proposed cell are 2.67× and 1.98× higher than the conventional 6T cell with 1.53× area overhead. Moreover, the improved soft error tolerance and better reliability against negative bias temperature instability (NBTI) of proposed 11T SRAM cell as compared to other considered cells make it suitable for the bio medical implant. A low-power double adjacent bit error detection and correction (DAEDC) scheme is proposed to further improve the robustness of designed 1 Kb bit-interleaved memory against the soft error occurrence. The leakage power of proposed cell is controlled by the stacking devices used in its cross-coupled inverter pair and the column based read ground signal (RGND) further controls the unnecessary bit line switching power of the array.

  • 27.
    Shastri, Anish
    et al.
    International Institute of Information Technology (IIIT) - Hyderabad, India.
    Jain, Vivek
    International Institute of Information Technology (IIIT) - Hyderabad, India.
    Chaudhari, Sachin
    International Institute of Information Technology (IIIT) - Hyderabad, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Werner, Stefan
    Norwegian University of Science and Technology (NTNU), Trondheim, Norway.
    Improving Accuracy of the Shewhart-based Data-Reduction in IoT Nodes using Piggybacking2019In: IEEE 5th World Forum on Internet of Things: Conference Proceedings, IEEE, 2019, p. 943-948Conference paper (Refereed)
    Abstract [en]

    This paper proposes the use of Shewhart test to reduce the number of data-transmissions in IoT networks. It is shown to outperform the widely-used least mean square (LMS) based data reduction method in terms of the number of data-transmissions, implementation complexity and mean square error (MSE) in prediction of time-series data at the sink node based on the partial transmissions of the measured time-series data from the sensor node. The paper also proposes the use of piggybacking and interpolation to further reduce the MSE of the estimated time-series data at the sink node without increasing the number of packet transmissions. The time-series data used for the comparison of data reduction algorithms is a set of measured temperature values in indoor and outdoor scenarios for four days using custom-designed wireless sensor nodes. To express the effectiveness of the piggybacked transmissions on battery lifetime, the total current consumption of the sensor node is measured for different number of piggybacks and corresponding battery lifetime is estimated. It is shown that the proposed piggyback approach significantly reduces the MSE at the cost of slight decrease in battery-lifetime.

  • 28.
    Shastri, Anish
    et al.
    Signal Processing and Communication Research Center International Institute of Information Technology - Hyderabad, India.
    Jain, Vivek
    Signal Processing and Communication Research Center International Institute of Information Technology - Hyderabad, India.
    Singh, Rhishi Pratap
    Signal Processing and Communication Research Center International Institute of Information Technology - Hyderabad, India.
    Chaudhari, Sachin
    Signal Processing and Communication Research Center International Institute of Information Technology - Hyderabad, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    On the Implementation of LMS-based Algorithm for Increasing the Lifetime of IoT Networks2018In: 2018 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS), IEEE, 2018Conference paper (Refereed)
    Abstract [en]

    This paper focuses on the customized-wireless sensor node implementation of the classical least mean square (LMS) algorithm for the reduction in data-transmissions from the sensor nodes to the sink in internet of things (IoT) networks. This reduction, in turn, increases the battery life of the sensor node. The system was deployed in outdoor and indoor environments to read the ambient temperature and then perform the prediction of the sensed data in order to minimize the number of data-transmissions to the sink node. The utility of the proposed concept has been demonstrated using the measured data and the battery life is increased 2.64 and 2.53 times in indoor and outdoor environments, respectively.

  • 29.
    Siddiqui, J.A.
    et al.
    Department of Electronics, Medi-Caps University, A.B. Road, Pigdamber Rau, Indore-453331 Indore Madhya Pradesh, India.
    Patil, S.
    Department of Electronics, Medi-Caps University, A.B. Road, Pigdamber Rau, Indore-453331 Indore Madhya Pradesh, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Wuriti, S.
    Department of Mathematics, K.L. University, Vaddeswaram, AP 522502, India.
    Arora, V.
    RBU, Punjab, India.
    Mulaveesala, R.
    Indian Institute of Technology Ropar, Bara Phool, Birla Seed Farms, Rupnagar, Punjab 140001, India.
    Efficient pulse compression favourable thermal excitation scheme for non-destructive testing using infrared thermography: a numerical study2020In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 56, no 19, p. 1003-1005Article in journal (Refereed)
    Abstract [en]

    Active thermal non-destructive testing (TNDT) has emerged as a swift, robust and cost-effective non-contact inspection method used to detect the surface and sub-surface defects present in a wide verity of solid materials. To further increase the efficacy of the process, various pulse-compression-based post-processing techniques are in use. However, the applicability of pulse compression-based thermographic methods has limited due to the presence of side lobes that degrades the energy concentration capabilities within the main lobe. In order to address this limitation, this work proposes a poly-phase code (P4-code). P4 codes are very efficient and robust in the reduction of distribution of energy in side lobes by concentrating on the main lobe. This Letter proposes a numerical study on the applicability of P4 codes-based pulse compression favourable thermal wave imaging approach for TNDT for testing and evaluation of steel specimen for identification of flat-bottom hole defects located at different depths. Further performance of the proposed method is compared with the widely used linear frequency modulated thermal wave imaging by considering the signal-to-noise ratio as a figure-of-merit.

  • 30.
    Yadav, Divya
    et al.
    NIT Jalandhar, India.
    Chouhan, Shailesh Singh
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Vishvakarma, S.K.
    Indian Institute of Technology, Indore India.
    Raj, Balwinder
    NIT Jalandhar India.
    Application Specific Microcontroller Design for Internet of Things Based Wireless Sensor Network2018In: Sensor Letters, ISSN 1546-198X, E-ISSN 1546-1971, Vol. 16, no 5, p. 374-385Article in journal (Refereed)
    Abstract [en]

    Today sensors are all over the place. We undervalue it, yet there are sensors in our vehicles, in our advanced cells, in processing plants controlling CO2 discharges, and even in the ground observing soil conditions in vineyards. WSN surprisingly cover the broad area of applications, and research and technology advance continuously increase their application field. The internet of things (IoT) introduced in correspondence to WSNs. WSN was traditionally recognized fundamental enabler for the IoT standard. WSNs make IoT applications valuable for both sensing and actuation. In this paper we design the microcontroller specifically for IoT based wireless sensor network. It takes the data from the different sensor node and send it to the gateway sensor node. We also design the Serial communication Peripheral (SPI) so that fast data transmission can be obtained very easily. Internal memory is used in the controller to hold the data for a short period, and then it is transmitted to the other wireless sensor node.

1 - 30 of 30
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