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  • 1.
    Nilsson, Joakim
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Imperial Coll, Dept Phys, London SW7 2AZ, England.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Correction: Maximal Q Factor for an On-Chip, Fuse-Based Trimmable Capacitor2019In: Electronics, ISSN 2079-9292, Vol. 8, no 6, article id 688Article in journal (Refereed)
  • 2.
    Nilsson, Joakim
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Imperial Coll, Dept Phys, London SW7 2AZ, England.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Maximal Q Factor for an On-Chip, Fuse-Based Trimmable Capacitor2019In: Electronics, ISSN 2079-9292, Vol. 8, no 1, article id 62Article in journal (Refereed)
    Abstract [en]

    This paper presents a circuit for realising a fuse-programmable capacitor on-chip. The trimming mechanism is implemented using integrated circuit fuses which can be blown in order to lower the resulting equivalent capacitance. However, for integrated circuits, the non-zero fuse resistance for active fuses and finite fuse resistance for blown fuses limit the Q factor of the resulting capacitor. In this work, we present a method on how to arrange the fuses in order to achieve maximal worst-case Q factor for the given circuit topology given the process parameters and requirements on capacitance. We also analyse and discuss the accuracy and limitations of the topology with regard to fuse resistance and parasitic elements such as bond pads.

  • 3.
    Nilsson, Joakim
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab. Imperial College London.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Chip-Coil Design for Wireless Power Transfer in Power Semiconductor Modules2018In: 2018 2nd Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA), Piscataway, NJ: IEEE, 2018Conference paper (Refereed)
    Abstract [en]

    This paper presents electromagnetic simulations of a wireless power transfer system suitable for a monitoring system for detection of solder fatigue in power semiconductor modules. Power is provided wirelessly from a printed spiral coil on a printed circuit board to a silicon chip with an on-chip coil. We use and adapt a known gradient-ascent-based optimisation algorithm to obtain suitable coil geometries. For a frequency of 433 MHz, the simulations show an efficiency of -34.7 dB which we conclude is sufficient for the proposed monitoring system.

  • 4.
    Renbi, Abdelghani
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Extracting the Magnetic Properties of Blast Furnace Cokes2018In: IET Science, Measurement & Technology, ISSN 1751-8822, E-ISSN 1751-8830Article in journal (Refereed)
    Abstract [en]

    This work aims to extract the magnetic properties of cokes used in the furnaces of the Swedish mineral company LKAB.Using Nicolson-Ross-Weir (NRW) algorithm and 10 sample loads of cokes, It has been found that cokes cause an attenuation of0.18 to 4 dB/m and exhibit between 2.8 and 3.7 as mean of magnetic permeability and between 0.075 and 0.11 as mean of losstangent within 10 to 350 MHz. With these figures, cokes will absorb 7.5 to 11 % of the reactive magnetic field energy and convertit to eddy currents due its natural electrical conductivity. The measurements are performed at room temperature.

  • 5.
    Borg, Johan
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Delay insensitive signal-injection calibration for large antenna arrays using passive hierarchical networks2017In: IEEE Transactions on Antennas and Propagation, ISSN 0018-926X, E-ISSN 1558-2221, Vol. 65, no 1, p. 190-195, article id 7747455Article in journal (Refereed)
    Abstract [en]

    Efficient beamforming of phased-array antennas requires that the phase delay of each channel is accurately known. One technique for achieving this is to distribute a calibration or local-oscillator reference signal through a delay-insensitive signal distribution network. In this paper, we propose using passive hierarchical signal distribution networks to distribute such signals, a method that scales significantly better with the size of the array than existing signal distribution methods. We analyze the impact of impedance variations within the network on the phase accuracy and propose a calibration front-end architecture. This front end also enables the return loss and coupling between antennas to be monitored for diagnostic purposes. We present an implementation of this front end that was applied to a small prototype antenna array, and show that this implementation exhibited low sensitivity to delays within the calibration network, reduced the temperature-dependent phase error of the front ends substantially, and can be used for performing antenna return-loss measurements

  • 6.
    Nilsson, Joakim
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Department of Physics, Imperial College, London.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    High-temperature characterisation and analysis of leakage-current-compensated, low-power bandgap temperature sensors2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 93, no 1, p. 137-147Article in journal (Refereed)
    Abstract [en]

    This paper analyses leakage current compensation techniques for low-power, bandgap temperature sensors. Experiments are conducted for circuits that compensate for collector-substrate, collector-base, body-drain and source-body leakage currents in a Brokaw bandgap sensor. The sensors are characterised and their failure modes are analysed at temperatures from 60 to 230∘C">230 ∘ C 230∘C . It is found that the most appropriate compensation circuit depends on the accuracy requirements of the application and on whether a stable reference voltage is required by other parts of the circuit. Experiments show that the power consumption is dominated by leakage current at high temperatures. One type of sensor was seen to consume 260 nW at 60∘C">60 ∘ C 60∘C , 2.1μW">2.1μW 2.1μW at 200∘C">200 ∘ C 200∘C and 14μW">14μW 14μW at 230∘C">230 ∘ C 230∘C . This work is motivated by the need to accurately monitor the temperature of power semiconductors in order to predict emerging faults in power semiconductor modules, a task for which cheap, single-chip, low-power, high-temperature, wireless bandgap temperature sensors are appropriate.

  • 7.
    Barabash, Victoria
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Space Technology.
    Ejemalm, Johnny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Space Technology.
    Kuhn, Thomas
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Space Technology.
    Milz, Mathias
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Space Technology.
    Molin, Sven
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Westerberg, Lars-Göran
    Luleå University of Technology, Department of Engineering Sciences and Mathematics, Fluid and Experimental Mechanics.
    Masters Programs in Space Science and Engineering in Northern Sweden2017Conference paper (Refereed)
  • 8.
    Delsing, Jerker
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    van Deventer, Jan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Eliasson, Jens
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Löfqvist, Torbjörn
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Sandin, Fredrik
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Concepts and Architecture for a Thumb-Sized Smart IoT Ultrasound Measurement System2016In: IEEE Ultrasonic Symposium 2016, Piscataway, NJ: IEEE conference proceedings, 2016Conference paper (Refereed)
    Abstract [en]

    This paper presents the technology concepts for a “thumb”-sized self-contained ultrasonic IoT measurement sys- tem. An overall architecture is proposed, and key elements are discussed with solutions using existing technology, thus arguing that realization is possible with the current technology.

    Such an ultrasonic IoT measurement system is constrained by its size and available energy, although it requires at least decent computational and communication resources. Because streaming data from such a device is not advisable from an energy viewpoint, there is a need for resource efficient (energy, memory and computational power) data analysis.

    An architecture with the following parts as well as some implementation details and performance data are proposed here:

    • Energy supply, battery and super capacitor

    • Transducer excitation achieving almost zero electrical losses

    • Event detection sensor interface

    • Data aggregation using sparse approximation and learned

      feature dictionaries, adapted to resource constrained em-

      bedded systems

    • IoT communication protocols and implementations enabling

      event -based communication and System of Systems integra- tion capabilities

      The optimization of system level performance requires each subsystem to be optimized for the specific measurement situation taking into account the subsystem interdependencies. This can be performed using a combined electrical and acoustical model of the system. Here, the model allowing electronic and acoustic co-simulation using SPICE is an important tool bridging the electronic and acoustic domains. 

  • 9.
    Johansson, Jonny
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Encapsulation method for smallwireless measurement systems in high temperature environments2016Conference paper (Refereed)
    Abstract [en]

    This paper presents an encapsulation concept that enables the construction of small wireless measurement systems that can operate in industrial environments with ambient temperatures of up to 1200°C. To maximize operational time and minimize size, a layer of thermal insulation is combined with water absorbed in a porous material in the core of the device. The simulated operating time before all of the frozen water at 0?C has transformed into steam at 100°C when the ambient temperature of the device was 1200°C is 21 minutes for a sphere with an outer radius of 4 cm. If the outer radius is increased to 10 cm the simulated operating time increases to 125 minutes. Measurements were performed to validate the design. When a sphere with a radius of 4 cm was subjected to an oven temperature of 1200°C the device held the core temperature at or below 101°C for a total of 25 minutes. The time to reach the boiling point of the water was 9 minutes. Thereafter, the temperature was held constant at 100 +/- 1°C for an additional 16 minutes whereafter a rapid rise in temperature took place once all water had evaporated.

  • 10.
    Fischer, Julia
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    High frequency limitations of active rectifier circuits for RFID applications2016In: 2016 MIXDES: 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, Poland, 23-25 June 2016, Piscataway, NJ: IEEE Communications Society, 2016, p. 326-329, article id 7529757Conference paper (Refereed)
    Abstract [en]

    This paper analyses the frequency limitations of an active rectifier for RFID applications that has been optimised for 13.56 MHz. The rectifier utilises an active MOS diode with threshold cancellation and a control scheme to reduce reverse leakage. The rectifier is implemented in AMS 0.35 µm CMOS and simulated in Cadence Spectre. For an input voltage of 2 V and an output current of 20 µA, a power and voltage conversion efficiency of 83 % and 89 %, respectively, are achieved at 13.56 MHz. We show that reducing the width of the main MOS transistor from 90 to 60 µm improves the upper frequency limit, but beyond 30 MHz the finite speed of the threshold cancellation control circuit limits the efficiency of the rectifier circuit.

  • 11.
    Rabén, Hans
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    A CMOS Front-end for RFID Transponders Using Multiple Coil Antennas2015In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 83, no 2, p. 149-159Article in journal (Refereed)
    Abstract [en]

    A front-end architecture for inductive RFID transponders using multiple coil antennas for reduced ori- entation sensitivity is presented. The front-end uses multiple antennas for reception and one antenna for transmission. A select function identifies the antenna that is most favorably oriented toward the reader for transmission by comparing the DC charge-up phases of multiple DC generation blocks during power-up of the transponder. CMOS circuit design and simulation results of a front-end for 125 kHz FSK modulation are presented for a pulsed RFID system as well as an archi- tecture for cascaded DC generation. This paper also includes an example of a coil antenna for spherical transponders using three independent orthogonal windings.

  • 12.
    Nilsson, Joakim
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Leakage Current Compensation for a 450 nW, High Temperature, Bandgap Temperature Sensor2015In: Proceedings of the 19th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2015, Piscataway, NJ: IEEE Communications Society, 2015, p. 343-347, article id 7208540Conference paper (Refereed)
    Abstract [en]

    The design of a 450 nW bandgap temperature sensor in the 0 to 175 °C range is presented. The design demonstrates a leakage current compensation technique that is useful for low-power designs where transistor performance is limited. The technique mitigates the effects of leakage in Brokaw bandgap references by limiting the amount of excess current that is entering the bases of the main bipolar pair due to leakage. Using this technique, Monte Carlo simulations show an improvement factor of 7.6 for the variation of the temperature sensitivity over the full temperature range. For the variation of the reference voltage, Monte Carlo simulations show an improvement factor of 2.3.Sensors built using this technique can be used to accurately monitor the temperature of power semiconductors since wireless temperature sensors become feasible with sufficiently low power consumption.

  • 13.
    Nilsson, Joakim
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Single Chip Wireless Condition Monitoring of Power Semiconductor Modules2015In: Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015, Piscataway, NJ: IEEE Communications Society, 2015, article id 7364407Conference paper (Refereed)
    Abstract [en]

    A concept for doing accurate monitoring of temperature in power semiconductor modules is proposed. The concept involves glueing wireless single-chip temperature sensors with on-chip coils in direct contact with power semiconductor devices within their modules. Direct contact results in accurate temperature measurements while wireless technology such as RFID provides galvanic isolation from the power devices. An overview of the electromagnetic situation within wire bond power semiconductor modules is presented and a prototype chip with an on-chip coil has been manufactured as an initial attempt to investigate the feasibility of the concept. Measurements on said chip provides some insight in the challenges in on-chip coil designs. The feasibility of the concept is supported by earlier work that have demonstrated high power transfer efficiencies and a low power temperature sensor that is able to operate at high temperatures.

  • 14.
    Beckman, Claes
    et al.
    Department of Communications systems, School of ICT, Royal Institute of Technology, Kista.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Tecsor, Irina
    Department of Communications systems, School of ICT, Royal Institute of Technology, Kista.
    Design considerations for the EISCAT-3D phased array antenna2014In: 2014 8th European Conference on Antennas and Propagation: (EuCAP); The Hague; Netherlands, 6 -11 April 2014, Piscataway, NJ: IEEE Communications Society, 2014, p. 1700-1704Conference paper (Refereed)
    Abstract [en]

    This paper presents a background and an overview of the initial design considerations for phased array antenna being designed for the New Generation multi-static, incoherent-scatter radar station - EISCAT-3D - in Northern Scandinavia. Its anticipated electrical, mechanical and environmental design requirements are given both by the physics as well as by the extreme climate in the subarctic region of northern Scandinavia

  • 15.
    Rabén, Hans
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Design of voltage multipliers for maximized DC generation in inductively coupled RFID tags2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 11, p. 3309-3317Article in journal (Refereed)
    Abstract [en]

    This paper presents models, circuit solutions and design procedures for maximized DC generation in inductively coupled RFID tags. An analytical model for the DC generation is derived, and relationships between the received signal in the tag coil antenna and the generated DC supply voltage using a voltage multiplier, based on both passive and active diodes, are presented. Derived from the trade-off between voltage gain in the multiplier and the tag coil at resonance, an equation for the optimum number of multiplier stages to achieve maximized DC generation is presented. Based on the derived equation, design examples are included with two typical tag coil antennas given a specification of the DC supply voltage and current. Also included in this paper is the design of a voltage multiplier based on active diodes implemented and manufactured in AMS 0.35 $mu{rm m}$ CMOS process. The active diodes are based on a concept of threshold cancellation of MOS diodes and make use of reverse leakage control to achieve full threshold cancellation.

  • 16.
    Ekman, Jonas
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Lindgren, Per
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    De Lauretis, Maria
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Lindner, Marcus
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Nilsson, Joakim
    Projekt: Frekvensomriktares funktion i beredskapskritiska system2014Other (Other (popular science, discussion, etc.))
    Abstract [sv]

    Vid dödnätstart av produktionsanläggningar och drift av svaga nät eller ö-drift är frekvensomriktare som driver pumpar och fläktar kritiska komponenter. Om frekvensomriktare påverkas av störningar i nätet kan elproduktion kopplas bort och det svaga nätet eller ö-driften kollapsa. Projektet ska studera frekvensomriktare ur ett antal aspekter såsom uppbyggnad, styrning och implementering i syfte att utveckla mer robusta frekvensomriktare och implementering av dessa för att säkerställa drift av svaga nät och ö-drift och minimera ytterligare driftstörningar vid svåra påfrestningar på elnätet.

  • 17.
    Tanveer, Muhammad
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Time stretcher for a time-to-digital converter with a precisely matched current mirror2014In: 2014 IEEE International System on Chip Conference (SOCC 2014): Las Vegas, 2-5 September 2014, Piscataway, NJ: IEEE Communications Society, 2014, p. 225-230, article id 6948932Conference paper (Refereed)
    Abstract [en]

    This paper presents an approach for the design ofa time stretcher based on charging and discharging a capacitorby currents with a ratio equal to the desired stretch factor. Thestretched time interval can be measured by using a time-to-digitalconverter to achieve improved system resolution. Expressionsfor the current source output impedance and transistor arearequired to reach a specified linearity and matching are derived.The realization uses wide-swing current mirrors to achieve therequired output impedance at an acceptable voltage swing at thecapacitor. The derived expressions and the overall design arevalidated with schematic and extracted simulations in a 0.35 μmCMOS process technology.

  • 18.
    Tanveer, Muhammad
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Nissinen, Ilkka
    Department of Electrical Engineering, University of Oulu.
    Nissinen, Jan
    Department of Electrical Engineering, University of Oulu.
    Kostamovaara, Juha
    Department of Electrical Engineering, University of Oulu.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Time-to-digital converter based on analog time expansion for 3D time-of-flight cameras2014In: Image Sensors and Imaging Systems 2014 / [ed] Ralf Widenhorn; Antoine Dupret, SPIE - International Society for Optical Engineering, 2014, article id 90220AConference paper (Refereed)
    Abstract [en]

    This paper presents an architecture and achievable performance for a time-to-digital converter, for 3D time-of-flight cameras. This design is partitioned in two levels. In the first level, an analog time expansion, where the time interval to be measured is stretched by a factor k, is achieved by charging a capacitor with current I, followed by discharging the capacitor with a current I/k. In the second level, the final time to digital conversion is performed by a global gated ring oscillator based time-to-digital converter. The performance can be increased by exploiting its properties of intrinsic scrambling of quantization noise and mismatch error, and first order noise shaping. The stretched time interval is measured by counting full clock cycles and storing the states of nine phases of the gated ring oscillator. The frequency of the gated ring oscillator is approximately 131 MHz, and an appropriate stretch factor k, can give a resolution of ≈ 57 ps. The combined low nonlinearity of the time stretcher and the gated ring oscillator-based time-to-digital converter can achieve a distance resolution of a few centimeters with low power consumption and small area occupation. The carefully optimized circuit configuration achieved by using an edge aligner, the time amplification property and the gated ring oscillator-based time-to-digital converter may lead to a compact, low power single photon configuration for 3D time-of-flight cameras, aimed for a measurement range of 10 meters

  • 19.
    Tanveer, Muhammad
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Nissinen, Ilkka
    Department of Electrical Engineering, University of Oulu.
    Nissinen, Jan
    Department of Electrical Engineering, University of Oulu.
    Kostamovaara, Juha
    Department of Electrical Engineering, University of Oulu.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Time-to-Digital Converter using an Analogue Time Stretcher for 3D Time of Flight Camera2014Conference paper (Refereed)
    Abstract [en]

    This paper describes an architecture and achievable performance of a time-to-digital converter by cascading a time stretcher and a gated ring oscillator based time-to-digital converter (GRO-TDC). The analogue time expansion, where the time interval to be measured is stretched by a factor k, is realized by charging a capacitor with a current I followed by discharging the capacitor by a current I/k . The currents are created by wide swing cascode current source/sinks with a current ratio of k. The time stretching method involves two conversions: time to charge and then charge to time. Whereas these are performed in each individualpixel, the final time to digital conversion is performed by the global GRO-TDC, where a multiphase gated ring oscillator is used to measure the stretched time interval by counting full clock cycles and storing the states of the ring oscillator within the clock period to obtain increased resolution. A block diagram of the proposed structure is shown paper.The nine phase single ended gated ring oscillator operates as an interpolator and as a clock during charge to time conversion. The layout of the gated inverters in the oscillator is designed by placing them in an order to compensate for the parasitic loading of capacitance for each stage and to minimize the effects of process variations. The clock of the 8-bit ripple counter is enabled at the start of the charge to time conversion by the Start-Stretch signal. The result of the counter will be ready after the clock of the counter is disabled to the counter by the Stop-Stretch timing mark from the comparator. Special attention is paid to the design of the hysteresis based comparator using positive feedback. The comparator is designed to achieve acceptable robustness against transistor mismatch, small power dissipation, offset voltage, linearity, speed, small area and good noise immunity. The digital flip-flops functioning as an interpolator will store the time interval measurement responses with in the clock cycle. By selecting an appropriate stretch factor and suitable clock frequency for the gated ring oscillator, measurement error of few cm in distance is achievable. To ensure reliable recording of the timing signals, the counter is synchronized by usinga dual edge synchronization scheme where one of the two flip-flops always has enough delay between data change and clock edge to avoidmetastability problems.

  • 20.
    Ekman, Jonas
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Lindgren, Per
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Variable-Frequency Drives: Three perspectives2014Conference paper (Refereed)
  • 21.
    Rabén, Hans
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    A discrete model of the DC charge-up phase in RFID rectifiers2013In: Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems: MIXDES 2013; Gdynia; 20 June 2013 through 22 June 2013, Piscataway NJ: IEEE Communications Society, 2013, p. 341-345, article id 6613370Conference paper (Refereed)
    Abstract [en]

    This paper presents a discrete model of the DC charge-up phase in a single MOS diode rectifier for an inductively coupled RFID system. The model was derived for a rectifier driven by a coil antenna and with a storage capacitor connected to the output. A comparison between the model and a simulation of a rectifier implemented in a 0.35 μm CMOS process demonstrated fast and accurate modeling of the charge up-phase for both LF and HF RFID applications. The model was used to determine the relationship between the voltage induced in the coil antenna and the available chip current based on a specification for the durations of the charge-up and the data-communication phases in a typical LF RFID application.

  • 22.
    Delsing, Jerker
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    New architecture for efficient data sampling in Wireless Sensor Network Devices2013Conference paper (Refereed)
    Abstract [en]

    When discussing powering wireless sensor net- work nodes, there are a few major energy consumers: com- munications, microcontroller and the sensor. We propose a wireless sensor network platform architecture minimizing the energy consumption of sensing. The architecture proposed herein is based on a reactive approach to sensing. A number of possible hardware approaches are evaluated and compared. This comparison indicates that analog storage between the sensing element and the sensor electronics can be a feasible method for reducing the energy consumption of the system.

  • 23.
    Rabén, Hans
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    A model for MOS diodes with vth-cancellation in RFID rectifiers2012In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 59, no 11, p. 761-765Article in journal (Refereed)
    Abstract [en]

    A theoretical model for diode-connected MOS transistors with a threshold cancellation technique is developed. The model is based on a detailed analysis of the technique with internal threshold cancellation (ITC) and reveals design insight and performance limitations. Derived design equations illustrate the tradeoff between the voltage drop and the reverse leakage of the diode. Furthermore, a design procedure for the optimization of the power conversion efficiency (PCE) of a bridge rectifier with ITC MOS diodes was developed based on the model. A rectifier was designed and implemented in an austriamicrosystems 0.35-$muhbox{m}$ CMOS process, and Cadence simulation results of the PCE and the voltage conversion efficiency show good agreement with the model.

  • 24.
    Rabén, Hans
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    An active MOS diode with V th-cancellation for RFID rectifiers2012In: 2012 IEEE International Conference on RFID (RFID 2012): Orlando, Florida, USA, 3 - 5 April 2012, Piscataway, NJ: IEEE Communications Society, 2012, p. 54-57Conference paper (Refereed)
    Abstract [en]

    An active MOS diode for low voltage and low power RFID rectifiers is presented. The diode is based on the technique with internal threshold cancellation (ITC) for MOS diodes and uses a simple control scheme to minimize the diode reverse leakage so that full threshold cancellation is achieved. A theoretical background that illustrates the limitations with the ITC diode and a detailed presentation of the proposed diode with a short design procedure is included. The proposed diode is implemented in AMS 0.35 μm CMOS and simulated in Cadense Spectre in a single diode rectifier. With a diode voltage ranging from 50 to 100 mV, the proposed diode simultaneously demonstrates improved voltage and power conversion efficiency of more than 20 % each for frequencies up to 1 MHz, as compared to the MOS diode with internal threshold cancellation.

  • 25.
    Borg, Johan
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    An ultrasonic transducer interface IC with integrated push-pull 40 Vpp, 400 mA current output, 8-bit DAC and integrated HV multiplexer2011In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 46, no 2, p. 475-484Article in journal (Refereed)
  • 26.
    Delsing, Jerker
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Architecture for extreme low power sensing in wireless sensor network devices2011In: SENSORCOMM 2011: The Fifth International Conference on Sensor Technologies and Applications, International Academy, Research and Industry Association (IARIA), 2011, p. 157-160Conference paper (Other academic)
    Abstract [en]

    When discussing powering wireless sensor network nodes, there are a few major energy consumers: communications, microcontroller and the sensor. We propose a wireless sensor network platform architecture minimizing the energy consumption of sensing. The architecture proposed herein is based on a reactive approach to sensing. A number of possible hardware approaches are evaluated and compared. This comparison indicates that analog storage between the sensing element and the sensor electronics can be a feasible method for reducing the energy consumption of the system.

  • 27.
    Borg, Johan
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Evaluation of a surface-channel CCD manufactured in a pinned active-pixel-sensor CMOS process2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 8, p. 2660-2664Article in journal (Refereed)
    Abstract [en]

    This paper presents measurements on a surfacechannel CCD with gates implemented using single-layer polysilicongates. The device was manufactured in a 0.18 μm PINNEDphoto diode CMOS process commercially available from UMC.The CCD was built with a field-plate covering all gates as wellas the space between them, which allows the potential in the gapbetween non-overlapping gates to be manipulated.We present charge transfer efficiency measurements performedat clock frequencies of 1 MHz and 5 MHz, at multiplebackground packet sizes, and field-plate voltages. We furtherpropose and apply a method for separating CTI in four-phaseCCDs due to trapping from the inefficiency stemming from otherphenomena.The measurements show a single stage CTI ranging from 1.7×10−4 with a moderate background charge and substantial fieldplatevoltage, to 0.007 at zero field-plate voltage and the highestbackground charge tested. The CTI can be reduced significantly(more than a factor of 10 in some cases) by applying a significantnegative voltage at the field-plate. This, and the fact that only aminor part of the CTI can be attributed to trapping, indicatesthat the performance of the device is limited by the presence ofpotential hollows in the gaps between the gates.

  • 28.
    Rabén, Hans
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Improved efficiency in the CMOS cross-connected bridge rectifier for RFID applications2011In: Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems: MIXDES 2011; Gliwice; 16 June 2011 through 18 June 2011, Piscataway, NJ: IEEE Communications Society, 2011, p. 334-339Conference paper (Refereed)
    Abstract [en]

    A bridge rectifier based on the cross-connected NMOS-PMOS bridge that avoids the inherent degradation of power conversion efficiency for increasing input levels is presented. Instead of PMOS switches, the proposed rectifier uses diode-connected MOS transistors with static threshold cancellation and minimised diode reverse leakage. With a simple and power efficient circuit solution the new rectifier allows for low-power, passive tag implementation in standard CMOS for both LF and HF RFID applications. Simulation results of the proposed rectifier in a 0.35 µm CMOS process show a power conversion efficiency over 60 % for all input levels above 0.75 V with a 100 kΩ load and an input signal frequency of 13.56 MHz. The simulated DC output voltage at the same conditions is approximately Vin - 0.3 V. A model for the PCE of the new rectifier that includes the impact of the Vth-generator is developed and compared with simulated results.

  • 29. Kozmin, Kirill
    et al.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Kostamovaara, Joha
    Oulu University.
    A low propagation delay dispersion comparator for a level-crossing AD converter2010In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 62, no 1, p. 51-61Article in journal (Refereed)
    Abstract [en]

    This paper presents the design of a continuous time voltage comparator with low propagation delay dispersion. The comparator is intended to be used as a building block for a level-crossing AD converter: a type of AD converter where the sampling moments are triggered when an input signal crosses predetermined threshold levels. This type of system sets very high demands on the time measurement and the comparator to achieve the desired performance. The comparator design is based on several techniques to minimize the comparator propagation delay dispersion. The comparator has been implemented in a 0.35 μm BiCMOS process. Measured results show good agreement with simulations. The slew rate related propagation delay dispersion is measured to 90 ps for an input frequency range from 3 to 10 MHz and amplitudes from 200 mV to 1.65 V. The comparator static power consumption is 9 mW.

  • 30.
    Wannberg, Gudmund
    et al.
    Swedish Institute of Space Physics / Institutet för rymdfysik.
    Andersson, H
    EISCAT Scientific Association, Kiruna.
    Behlke, R
    Auroral Observatory, University of Tromsö.
    Belyey, V
    Auroral Observatory, University of Tromsö.
    Bergqvist, Peter
    EISCAT Scientific Association, Kiruna.
    Borg, Johan
    Brekke, A
    Auroral Observatory, University of Tromsö.
    Delsing, Jerker
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Eliasson, L
    Swedish Institute of Space Physics / Institutet för rymdfysik.
    Finch, I
    Space Science and Technology Department, Rutherford Appleton Laboratory.
    Grydeland, T
    Auroral Observatory, University of Tromsö.
    Gustavsson, B
    Auroral Observatory, University of Tromsö.
    Häggström, I
    EISCAT Scientific Association, Kiruna.
    Harrison, R.A.
    Space Science and Technology Department, Rutherford Appleton Laboratory.
    Iinatti, T
    EISCAT Scientific Association, Kiruna.
    Johansson, Gustav
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, J
    Swedish Institute of Space Physics / Institutet för rymdfysik.
    Hoz, C La
    Auroral Observatory, University of Tromsö.
    Laakso, T
    EISCAT Scientific Association, Kiruna.
    Larsen, R
    EISCAT Scientific Association, Kiruna.
    Larsmark, Mikael
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Lindgren, Tore
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Nordenvaad, Magnus Lundberg
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Signals and Systems.
    Markkanen, J
    EISCAT Scientific Association, Kiruna.
    Wolf, I
    Swedish Institute of Space Physics / Institutet för rymdfysik.
    EISCAT_3D - a next-generation European radar system for upper atmosphere and geospace research2010In: Radio Science Bulletin, ISSN 1024-4530, no 332, p. 75-88Article in journal (Refereed)
    Abstract [en]

    The EISCAT Scientifi c Association, together with a number of collaborating institutions, has recently completed a feasibility and design study for an enhanced performance research radar facility to replace the existing EISCAT UHF and VHF systems. This study was supported by EU Sixth-Framework funding. The new radar retains the powerful multi-static geometry of the EISCAT UHF, but will employ phased arrays, direct-sampling receivers, and digital beamforming and beam steering. Design goals include, inter alia, a tenfold improvement in temporal and spatial resolution, an extension of the instantaneous measurement of full-vector ionospheric drift velocities from a single point to the entire altitude range of the radar, and an imaging capability to resolve small-scale structures. Prototype receivers and beamformers are currently being tested on a 48-element, 224 MHz array (the "Demonstrator") erected at the Kiruna EISCAT site, using the EISCAT VHF transmitter as an illuminator.

  • 31. Johansson, Gustav
    et al.
    Hägglund, Fredrik
    Carlson, Johan E.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Signals and Systems.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Picosecond level error detection using PCA in the hardware timing systems for the EISCAT_3D LAAR2010In: Radio Science Bulletin, ISSN 1024-4530, no 333, p. 45-50Article in journal (Refereed)
    Abstract [en]

    While developing the timing system for the receiver arrays for the EISCAT_3D system, several approaches to detect and adjust for timing errors within the array have been explored. The demand on the timing error between all elements in the array is to have a standard deviation of less than 120 ps, thus requiring high quality error detection systems to guarantee radar operation. This paper investigates the qualities of a secondary error detection system based on statistical analysis of captured data. The measurements are assembled with a Signal-to-Noise Ratio (SNR) of -30 dB implying that the elements in a 2112 element array need to be grouped into sub-arrays of 48 elements each. The captured data is then evaluated by Principal Component Analysis (PCA) and averaged over 20,000 measurements, or about half a second. Timing errors between sub-arrays of down to ~120 ps and a percentage of faulty sub-arrays of up to 20% are detectable. As a secondary error detection system PCA is cheap to implement since the only need of the analysis is a small amount of computer time. It also provides a valuable detection system for hardware errors in the primary timing system that can otherwise be hard to find.

  • 32. Johansson, Gustav
    et al.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Nordenvaad, Magnus Lundberg
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Signals and Systems.
    Wannberg, Gudmund
    Swedish Institute of Space Physics.
    Simulation of post-ADC digital beamforming for large aperture array radars2010In: Radio Science, ISSN 0048-6604, E-ISSN 1944-799X, Vol. 45, no RS3001Article in journal (Refereed)
    Abstract [en]

    This paper presents simulations and methods developed to investigate the feasibility of using a Fractional-Sample-Delay (FSD) system in the planned EISCAT_3D incoherent scatter radar. Key requirements include a frequency-independent beam direction over a 30 MHz band centered around 220 MHz, with correct reconstruction of pulse lengths down to 200 ns. The clock jitter from sample to sample must be extremely low for the integer sample delays. The FSD must also be able to delay the 30 MHz wide signal band by 1/1024th of a sample without introducing phase shifts, and it must operate entirely in baseband. An extensive simulation system based on mathematical models has been developed, with inclusion of performance-degrading aspects such as noise, timing error, and bandwidth. Finite Impulse Response (FIR) filters in the baseband of a band-pass-sampled signal have been used to apply true time delay beamforming. It has been confirmed that such use is both possible and well behaved. The target beam-pointing accuracy of 0.06° is achievable using optimized FIR filters with lengths of 36 taps and an 18 bit coefficient resolution. Even though the minimum fractional delay step necessary for beamforming is ∼13.1 ps, the maximum sampling timing error allowed in the array is found to be σ ≤ 120 ps if the errors are close to statistically independent.

  • 33.
    Johansson, Jonny
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Gustav
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Larsmark, Mikael
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Lindgren, Tore
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    EISCAT_3D: EISCAT 3D Radar Receiver/Antenna Subsystem Report2009Report (Other academic)
  • 34. Kozmin, Kirill
    et al.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Delsing, Jerker
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Level-crossing ADC performance evaluation toward ultrasound application2009In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 56, no 8, p. 1708-1719Article in journal (Refereed)
    Abstract [en]

    A performance evaluation of a level-crossing analog-to-digital converter (ADC) is presented. It is shown that its signal-to-noise ratio (SNR) does not depend on the input-signal amplitude, which results in an almost-flat SNR for amplitudes that fall into the Nyquist criteria for irregular sampling. The influence of the reconstruction procedure on SNR is discussed, and possible limitations due to the comparator and clock on the performance of the ADC are analyzed. This analysis allows for specification of comparator and clock parameters such that they do not limit the ADC performance yet are not overestimated. In conclusion, a previously known level-crossing ADC design procedure is extended.

  • 35. Johansson, Gustav
    et al.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Delsing, Jerker
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Lindgren, Per
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Öman, Joakim
    Sverige.
    Projekt: ESiS EP2009Other (Other (popular science, discussion, etc.))
    Abstract [sv]

    Sammanfattningsvis är forskningsmålet att optimera kretskortsproduktion för små och medelstora serier. Huvudsakligen handlar det om att undersöka och modellera det termiska systemet mellan kretskort och lödugn. Modellen kommer sedan att användas för att ge bättre konfigurationsparametrar för produktionslinjen. En bra modell kommer inte bara att öka lödningskvalitén och minska antalet kasserade kretskort men kan också även användas för att hitta avvikelser redan i kretskortsdesignen.

  • 36. Stenberg, Gustav
    et al.
    Lindgren, Tore
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    A picosecond accuracy timing system based on L1-only GNSS receivers for a large aperture array radar2008In: Proceedings of the 21th International Technical Meeting of the Satellite Division of the Institute of Navigation: ION GNSS 2008, 2008, p. 112-116Conference paper (Refereed)
    Abstract [en]

    During the development of EISCAT_3D, a Large Aperture Array Radar (LAAR), with direct sampling at each antenna element and constituted of up to 16.000 antenna elements, intended for atmospheric research, the need for a highly accurate timing system was recognized. This paper describes the method and test results of a GNSS based timing system on a 300 m scale formed on L1-only GNSS receivers.Simulations have shown that over a distance of 300 m the maximum allowed total timing jitter is 160 ps. This timing jitter is composed of jitter from the clock distribution, local oscillator, ADC and movement of the antenna phase center due to weather conditions. A reasonable assumption is that at most a third of the total jitter is generated in the clock distribution system, i.e. 50 ps. Such accuracy is impossible to achieve with the traditionally often used non-calibrated cable-based clock distribution system, even heating of clock distribution cables can alter the length of the cables to the extent that too large errors are generated, thus the choice to use a GNSS-based clock distribution system that is unaffected by such effects. Other benefits of building a GNSS timing system include lower cost due to reduced amount of coaxial cable throughout the array and the need for building a continuous cable length calibration system that ensures timing accuracy of the distributed clock system to the necessary levels. By dividing the LAAR into small sub-arrays of 9 elements each, the maximum length of the cables distributing the clock is reduced to 4.5 m which is short enough to be calibrated by length approximation only, assuming that the clock distributed to each sub-array is known. Inserting a GNSS receiver at all of these sub-arrays, to provide a clock reference that is unaffected by changing conditions over the array, each sub-array is now timed to the specified accuracy.In general, a GNSS L1-receiver is rated to produce a clock with an error of less than 50 ns, which is about 1000 times too high. However, unique conditions apply to this GNSS timing system that improvs the accuracy, such as:- A local system, i.e. the maximum distance between two GNSS antennas are 300 m which infer all significant atmospheric errors in this application to be common over the array.- A common highly accurate reference clock is distributed to all receivers, which removes the clock drift errors between the receivers.- Software based selection of satellites used for the timing solution to exclude timing errors from different matrices in the position and timing calculations.- All receivers are stationary which allow long integration times, up to 30 min because the time constant of the cable length change in the reference clock distribution is in that order of magnitudes, to improve accuracy- Phase measurements from one satellite only is sufficient to calculate the timing error between the sub-arrays since the relative position of each receiver is known. - No integer ambiguity solution is necessary, again, since the relative position of the receivers is known and the absolute time difference between the receivers is insignificant, only the phase of the distributed clock is important.Satisfying these conditions decreases the clock error from the GNSS receivers sufficiently to reach the necessary levels of accuracy.Each sub-array contains a Voltage Controlled Oscillator (VCO) in which the distributed clock is reproduced and distributed through a Delay Locked Loop (DLL) to the local GNSS receiver, the radar ADCs and a signal injection system located as close to the radar antennas as possible to calibrate the analogue signal path of the system. The purpose of the DLL is to adjust the phase of the reference clock to be equal throughout the array. This is achieved by creating a closed loop feedback from the GNSS receiver to the DLL and adjusting the phase according to the phase differences in the received satellite signals in respect to a reference GNSS receiver. This reference receiver is a high-end receiver which is used in conjunction with purpose specific software to produce information sent to each of the sub-array receivers necessary to calculate the expected phase of local VCO clock. Compared to the actual phase of the VCO, the DLL can now make the necessary adjustments to the reference clock. The information sent is; satellites to use, Doppler-shift, tracking chip and expected phase. This information allow the sub-array receivers to only be capable of tracking a low number of satellites, no more than 6, and using the tracked phase differences to calculate the expected phase of the local VCO. Thus, full capability receivers are not needed, but instead a Digital Signal Processor (DSP) is used with a GNSS RF-frontend to control the DLL and the Automatic Gain Control (AGC) of the RF-frontend.Test measurements have been performed in a real environment during windy winter conditions, clear weather at -10 C and wind speeds up to 20 m/s in gusts, with three antennas placed randomly, but precisely surveyed, at about 5 m distance from each other placed on a rooftop to simulate the conditions in the EISCAT_3D LAAR. IF data from the antennas were collected during a one hour measurement and then post-processed to calculate the expected phase differences between the antennas. These phase differences provide a direct measurement of the accuracy levels attainable. The test results show that when integrating over 15 min, a total clock distribution jitter of less than 50 ps is achievable with simple calculations that can be implemented into a DSP.

  • 37.
    Johansson, Jonny
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Incorporation of mechanical noise in the SPICE model of a piezoelectric transducer2008In: Proceedings of the International Congress on Ultrasonics: Vienna, April 9-13, 2007, International Congress on Ultrasonics , 2008Conference paper (Refereed)
    Abstract [en]

    SPICE models of a piezoelectric device and the ultrasound propagation medium can be used in a simulator intended for electronic circuits and IC design to make efficient system level optimizations. This paper presents the inclusion of mechanical noise in the SPICE model of an ultrasound system. The modeling of the noise is based on the mechanical thermal noise which is equivalent to electronic Johnson (thermal) noise. For a system with a high-Q piezoelectric device designed into a medium-Q transducer the main energy loss, and thus also the main noise contribution, will occur in backing and sound propagation media. Thus, the modeling of the mechanical noise is performed by including electrical noise generation in the resistors that model these media in the electrical equivalent circuit. The resulting output voltage noise follows theoretical derivations of transducer noise as published by Farlow and Hayward. Simulations of a 4 MHz Pz27 piezoelectric disc with a diameter of 8 mm give a peak spectral noise density over 1 nV / √Hz, which is comparable to that achievable with low-noise preamplifiers.

  • 38.
    Borg, Johan
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Optimization of the design of an integrated ultrasonic preamplifier2008In: Proceedings of the International Congress on Ultrasonics: Vienna, April 9-13, 2007, International Congress on Ultrasonics , 2008Conference paper (Refereed)
    Abstract [en]

    Traditionally BJT or BiCMOS amplifiers have been used to achieve equivalent input noise densities of 1 nV√Hz or less, as desirable in some ultrasonic applications. Due to an increasing demand on increased integration it can be necessary to implement the amplifier in a CMOS process. As part of this design process we applied the particle swarm optimization to the problem of optimizing an amplifier specifically for operation in the 2-4 MHz frequency band. We present measurements on the manufactured circuit with performance comparable to the best available BJT-based amplifiers available today.

  • 39. Kozmin, Kirill
    et al.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Comparator propagation delay dispersion minimization2007In: IEEJ International Analog VLSI Workshop Proceedings, Institute of Electrical Engineers of Japan , 2007, p. 160-165Conference paper (Refereed)
    Abstract [en]

    In most comparator designs, a signal is preamplified before it is fed to the decision circuit which actually makes comparison. It is also desirable that the total comparator propagation delay, as well as its dispersion, is dominated by the delay and the dispersion of the preamplifier.This paper presents the analysis of the propagation delay in a multistage preamplifier and proposes a way to minimize the propagation delay dispersion by a non-even distribution of gain in the amplifier chain.

  • 40.
    Johansson, Jonny
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Larsmark, Mikael
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Lindgren, Tore
    Lundberg Nordenvaad, Magnus
    Luleå University of Technology, Department of Business Administration, Technology and Social Sciences, Business Administration and Industrial Engineering.
    Johansson, Gustav
    Ekman, Jonas
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Ståbis, Joel
    Sverige.
    Project: EISCAT 3D2007Other (Other (popular science, discussion, etc.))
  • 41.
    Johansson, Jonny
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Martinsson, Pär-Erik
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Signals and Systems.
    Delsing, Jerker
    Simulation of absolute amplitudes of ultrasound signals using equivalent circuits2007In: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, ISSN 0885-3010, E-ISSN 1525-8955, Vol. 54, no 10, p. 1977-1983Article in journal (Refereed)
    Abstract [en]

    Equivalent circuits for piezoelectric devices and ultrasonic transmission media can be used to cosimulate electronics and ultrasound parts in simulators originally intended for electronics. To achieve efficient systemlevel optimization, it is important to simulate correct, absolute amplitude of the ultrasound signal in the system, as this determines the requirements on the electronics regarding dynamic range, circuit noise, and power consumption.This paper presents methods to achieve correct, absolute amplitude of an ultrasound signal in a simulation of a pulse-echo system using equivalent circuits. This is achieved by taking into consideration loss due to diffraction and the effect of the cable that connects the electronics and the piezoelectric transducer. The conductive loss in the transmission line that models the propagation media of the ultrasound pulse is used to model the loss due to diffraction.Results show that the simulated amplitude of the echo follows measured values well in both near and far fields, with an offset of about 10%. The use of a coaxial cable introduces inductance and capacitance that affect the amplitude of a received echo. Amplitude variations of 60% were observed when the cable length was varied between 0.07 m and 2.3 m, with simulations predicting similar variations. The high precision in the achieved results show that electronic design and system optimization can rely on system simulations alone. This will simplify the development of integrated electronics aimed at ultrasound systems.

  • 42. Stenberg, Gustav
    et al.
    Borg, Johan
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Wannberg, Gudmund
    EISCAT Scientific Association, Kiruna.
    Simulation of post-ADC digital beam-forming for large area radar receiver arrays2007In: Proceedings: 2006 International RF and Microwave Conference : September 12 - 14, 2006, Putrajaya, Malaysia / [ed] Zaiki Awang, Piscataway, NJ: IEEE Communications Society, 2007, p. 272-276Conference paper (Refereed)
    Abstract [en]

    In order to provide instantaneous three-dimensional radar measurements spanning the entire vertical extent of the ionosphere, the planned EISCAT 3D incoherent scatter radar system includes multiple receive-only antenna arrays, situated at 90-280 km from the main transmit/receive site. These will employ band-pass sampling at ∼80 MHz, with the input signal spectrum contained in the 6th Nyqvist zone. This paper presents simulations and methods used to investigate use of a post-ADC fractional-sample-delay (FSD) system necessary to perform true time-delay beamforming. To test the feasibility and limitations of the system an extensive simulation tool has been developed. The simulation system is implemented in matlab to provide cross-platform compatibility and can be applied to any similar system. Performance degrading aspects such as noise, jitter, bandwidth and resolution can be included in the simulations. The use of FIR-filters in the base-band of a band-pass sampled signal to apply true time-delay beam-forming is shown to be feasible.

  • 43.
    Dorn, R.
    et al.
    Fraunhofer Institute for Integrated Circuits IIS, Am Wolfsmantel 33, 91058 Erlangen.
    Voelker, M.
    Fraunhofer Institute for Integrated Circuits IIS, Am Wolfsmantel 33, 91058 Erlangen.
    Neubauer, H.
    Fraunhofer Institute for Integrated Circuits IIS, Am Wolfsmantel 33, 91058 Erlangen.
    Hauer, H.
    Fraunhofer Institute for Integrated Circuits IIS, Am Wolfsmantel 33, 91058 Erlangen.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    A 3-channel ECG measuring system for wireless applications2006In: MeMeA 2006: 2006 IEEE International Workshop on Medical Measurement and Applications, Piscataway, NJ: IEEE Communications Society, 2006, p. 49-52Conference paper (Refereed)
    Abstract [en]

    This paper describes the design and impementation of an integrated frontend for electrocardiographic (ECG) systems, realized in a 0.35 μm 2P4M CMOS process. The performance is optimized to adhere to the standard IEC60601-2-47, which defines the requirements for safety and essential performance of ambulatory ECG equipment. The system consists of three channels to measure the 3 leads of a Goldberger ECG monitoring scheme, therefore a single ended design structure was chosen to minimize the power consumption. A fourth channel is included for additional measurements. Each of the four channels contains a low power multi-bit sigma-delta modulator and a low power digital filter. Three channels are equipped with a low noise preamplifier. The supply voltage can be varied from 2.4 Volt up to 3.6 Volt. With a total power consumption of less than 2 mW the circuit is designed for battery operated equipment.

  • 44.
    Voelker, M.
    et al.
    Fraunhofer Institute for Integrated Circuits IIS, Am Wolfsmantel 33, 91058 Erlangen.
    Neubauer, H.
    Fraunhofer Institute for Integrated Circuits IIS, Am Wolfsmantel 33, 91058 Erlangen.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Dorn, R.
    Fraunhofer Institute for Integrated Circuits IIS, Am Wolfsmantel 33, 91058 Erlangen.
    Hauer, J.
    Fraunhofer Institute for Integrated Circuits IIS, Am Wolfsmantel 33, 91058 Erlangen.
    A digital filter for mobile ECG measurement systems2006In: MeMeA 2006: 2006 IEEE International Workshop on Medical Measurement and Applications, Piscataway, NJ: IEEE Communications Society, 2006, p. 45-48Conference paper (Refereed)
    Abstract [en]

    This paper presents the design and implementation of an integrated digital filter for ambulatory ECG monitoring. The requirements given by the standard IEC60601-2-47 which covers ambulatory ECG equipment are met. The filter is designed to follow a three bit Delta Sigma Modulator and includes 512 times decimation. Measurements show that the average stop band attenuation is above 70 dB. The use of half band sub filters offers the possibility to move the decimation in front of them and hence reduce the power consumption. The power consumption of the filter is 2.7 μW at 51.2 kHz system clock.

  • 45. Kozmin, Kirill
    et al.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Constant gm, rail-to-rail input transconductance stage with output common mode current compensation2006In: 13th IEEE International Conference on Electronics, Circuits and Systems: ICECS '06 ; 10 - 13 Dec. 2006, Nice, France, Piscataway, N.J: IEEE Communications Society, 2006, p. 596-599Conference paper (Refereed)
    Abstract [en]

    This paper presents a compensation structure to reduce the output common mode current of a rail-to-rail constant gm transconductance stage. The transconductance stage is a differential structure with the input transistors biased in weak inversion. This results in low power consumption and a simple relation between gm and tail currents. The constant gm is achieved by doubling the tail current in the active differential couple when the other one goes to cut off. Together with constant bias current in the output stage this can result in common mode bias current flowing from the output depending on the common mode input voltage. The proposed solution eliminates this problem by variation of the bias current in the output stage in relation to the tail currents in the differential couples. The transconductance stage was manufactured in a 0.35 um CMOS process. Measurement results are presented together with simulation data. The compensation structure cancels the common mode output currents for common mode input signals up to a frequency of 7 MHz.

  • 46.
    Johansson, Jonny
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Delsing, Jerker
    Microelectronics mounted on a piezoelectric transducer: method, simulations, and measurements2006In: Ultrasonics, ISSN 0041-624X, E-ISSN 1874-9968, Vol. 44, no 1, p. 1-11Article in journal (Refereed)
    Abstract [en]

    This paper describes the design of a highly integrated ultrasound sensor where the piezoelectric ceramic transducer is used as the carrier for the driver electronics. Intended as one part in a complete portable, battery operated ultrasound sensor system, focus has been to achieve small size and low power consumption. An optimized ASIC driver stage is mounted directly on the piezoelectric transducer and connected using wire bond technology. The absence of wiring between driver and transducer provides excellent pulse control possibilities and eliminates the need for broad band matching networks. Estimates of the sensor power consumption are made based on the capacitive behavior of the piezoelectric transducer. System behavior and power consumption are simulated using SPICE models of the ultrasound transducer together with transistor level modelling of the driver stage. Measurements and simulations are presented of system power consumption and echo energy in a pulse echo setup. It is shown that the power consumption varies with the excitation pulse width, which also affects the received ultrasound energy in a pulse echo setup. The measured power consumption for a 16 mm diameter 4.4 MHz piezoelectric transducer varies between 95 μW and 130 μW at a repetition frequency of 1 kHz. As a lower repetition frequency gives a linearly lower power consumption, very long battery operating times can be achieved. The measured results come very close to simulations as well as estimated ideal minimum power consumption.

  • 47.
    Borg, Johan
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    van Deventer, Jan
    Delsing, Jerker
    Reciprocal operation of ultrasonic transducers: experimental results2006In: Proceedings: 2006 IEEE Ultrasonics Symposium : Vancouver, Canada, 3 - 6 October 2006, Piscataway, NJ: IEEE Communications Society, 2006, p. 1013-1016Conference paper (Refereed)
    Abstract [en]

    Ultrasonic transit-time flow-meters estimate fluid or gas flows from the difference in times of flight of upstream and downstream acoustic pulses. However, any delay differences arising from sources other than the flow to be measured will cause a troublesome "zero flow" offset error.In theory, the transducers used in the measurement system should not influence the zero flow error, as electroacoustic systems based on piezoelectric transducers have been shown to be reciprocal (when the media is stationary). However, care is required when designing the electrical interfaces for the piezoelectric transducers, if reciprocity in the system is to be utilized.This work presents technique and measurements that apply reciprocity to an ultrasonic transit-time flow-meter. Specialized electrical transducer interfaces with options to drive the transducers from either low or high impedance sources were used. Combined with a high-impedance receive mode these options made it possible to change the conditions for reciprocity in the system.We show reduced delay difference in 9 cases out of 10 when trying to utilize the reciprocal property compared to when we disregard it in favor for larger excitation energy. The delay improvements were accompanied by reduced differences between the center frequencies of the signals from the two paths.

  • 48.
    Delsing, Jerker
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Ekman, Jonas
    Johansson, Jonny
    Sundberg, Sofia
    Bäckström, Mats
    Swedish Defence Research Agency FOI, Division of Sensor Technology.
    Nilsson, T.
    Swedish Defence Research Agency FOI, Division of Sensor Technology.
    Susceptibility of sensor networks to intentional electromagnetic interference2006In: 2006 17th International Zurich Symposium on Electromagnetic Compatibility: Suntec City, Singapore, 28 February - 3 March 2006, Piscataway, NJ: IEEE Communications Society, 2006, p. 172-175Conference paper (Refereed)
    Abstract [en]

    It is reasonable to think that sensor networks might be part of society critical systems in the future. Therefor this paper discusses and shows the vulnerabilities of sensor networks to intentional electromagnetic interference (IEMI). Principle ways of sensor network IEMI is addressed and followed by a discussion on schemes for protection. Experimental results for both in-band and exband interference from low- and high- level sources is reported. It is obvious that more emphasis has to be put on sensor networks susceptibility to IEMI, and in particular more experimental data is needed.

  • 49. Gabert, A.
    et al.
    Borg, Johan
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Temperature stabilization of electronics module2006In: The IMAPS Nordic Annual Conference: September 17-19, 2006, Gothenburg, Sweden / [ed] Jarkko Kutilainen, Oslo: International Microelectronics and Packaging Society (IMAPS) Nordic, 2006, p. 97-103Conference paper (Refereed)
    Abstract [en]

    Outdoor applications of electronics modules expose the systems to harsh environmental conditions. When very high performance is required, it may be necessary to actively stabilize the temperature in the module. This paper presents a systematic approach to the problem of designing a temperature stabilized environment for medium size electronics modules. The target system is the front-end electronics for the antennas in the EISCAT-3D incoherent scatter radar system. The electronics have an estimated constant power dissipation of about 10 W. Initially simulations verified the design approach and gave valuable information of the heat distribution in the box over the range of target temperatures. The design was evaluated by making a prototype on which different measurements were performed, which gave a clear picture of the system functionality. Using two Peltier modules and an insulated box a temperature stability of ±0.02°C at 20°C over an ambient temperature range of -40°C to 40°C was achieved.

  • 50.
    Johansson, Jonny
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Gustafsson, Martin
    Delsing, Jerker
    Ultra-low power transmit/receive ASIC for battery operated ultrasound measurement systems2006In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 125, no 2, p. 317-328Article in journal (Refereed)
    Abstract [en]

    This paper describes the design of the complete transmit and receive electronics circuitry for a piezoelectric transducer in one single ASIC. The chip will be one building block in a thumb size battery operated ultrasound measurement system. The main design target has been to achieve extremely low power consumption while keeping the number of external components minimal. To overcome the dynamic range limitations imposed by a battery supply an on-chip boost converter uses one external inductor to generate up to 40 V for excitation of the transducer. The transducer itself is used as a storage capacitor, whereafter it is rapidly discharged to generate an ultrasound pulse. An on-chip amplifier with intermittent operation is controlled by a state machine and used to amplify incoming echoes. The chip has been fabricated in a 0.8 m high voltage CMOS process, with a total chip area of 12 mm2. Measurements verify the design approach. The power consumption for the system reaches within a factor of 2 of the power needed to charge the capacitance of the piezoelectric transducer from a fixed voltage source. The results show the possibility to achieve extremely low power consumption in a battery operated pulse–echo ultrasound measurement system.

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