This paper presents the design of a continuous time voltage comparator with low propagation delay dispersion. The comparator is intended to be used as a building block for a level-crossing AD converter: a type of AD converter where the sampling moments are triggered when an input signal crosses predetermined threshold levels. This type of system sets very high demands on the time measurement and the comparator to achieve the desired performance. The comparator design is based on several techniques to minimize the comparator propagation delay dispersion. The comparator has been implemented in a 0.35 μm BiCMOS process. Measured results show good agreement with simulations. The slew rate related propagation delay dispersion is measured to 90 ps for an input frequency range from 3 to 10 MHz and amplitudes from 200 mV to 1.65 V. The comparator static power consumption is 9 mW.

A performance evaluation of a level-crossing analog-to-digital converter (ADC) is presented. It is shown that its signal-to-noise ratio (SNR) does not depend on the input-signal amplitude, which results in an almost-flat SNR for amplitudes that fall into the Nyquist criteria for irregular sampling. The influence of the reconstruction procedure on SNR is discussed, and possible limitations due to the comparator and clock on the performance of the ADC are analyzed. This analysis allows for specification of comparator and clock parameters such that they do not limit the ADC performance yet are not overestimated. In conclusion, a previously known level-crossing ADC design procedure is extended.

Integrated circuit (IC) power consumption and die are two important parameters that can define its cost as well as performance. That is why these two topics remain very important both in industry and in the research community. The fact that many ICs are designed to work in autonomous electronic devices with a limited power supply makes power consumption a particularly important issue. The main focus of this thesis is to investigate how specific signal properties can be utilized in the design of power efficient, small die area data acquisition and signal conditioning systems. In a signal acquisition system, three main parts can typically be identified: signal sensing and conditioning, signal processing, and communication. All of these parts consume energy. To reduce power consumption, different strategies can be used. For instance, the parts that are unused can be shut down. Another strategy is to use an event driven approach for hardware design. In this approach, the necessary parts of the acquisition system are enabled in response to external or internal events. The present thesis shows how an event driven approach can be utilized in hardware design in an example of level-crossing ADC, where sampling moments are triggered by the signal itself. The thesis presents a design procedure for the level-crossing ADC. Constraints for each building block are identified in system level simulations, performed in Cadence and MATLAB. A particular focus was put on the design of a comparator -- one of the ADC blocks. One of the main parameters for the comparator, in the context of the level-crossing ADC, is the propagation delay stability. The thesis discusses several techniques, which can be used to improve the propagation delay stability. Furthermore, two comparator implementations are presented. System simulations show the feasibility of the level-crossing ADC. They also show that such an ADC has a potential to reach smaller required die area and power consumption in the range of state of the art conventional ADCs. Another example of the signal properties utilization, in order to reach a smaller design area, presented in the thesis is in a navigation system for mobile robots. The navigation system consists of CMOS image sensors, an infra-red flash, and reflecting beacons placed vertically on walls. After an image is taken, the beacons are detected on the image and the position of the robot is calculated. The vertical positioning of the beacons allows minimization of the computational effort for their detection in the image. The image sensor optics, however, introduces image distortion, which can result in systematic calculation error. The distortion can be calibrated and eliminated after the image is taken. This, however, requires some computation power, which can be unavailable either due to complexity or calculation time constraints. Therefore, a precalculated model can be stored in memory and applied later on. This approach, however, requires a large amount of memory. To reduce the required memory size, a compression algorithm based on distortion model properties is presented in the thesis. The algorithm allows reduction of the required memory by more than 100 times.

In most comparator designs, a signal is preamplified before it is fed to the decision circuit which actually makes comparison. It is also desirable that the total comparator propagation delay, as well as its dispersion, is dominated by the delay and the dispersion of the preamplifier.This paper presents the analysis of the propagation delay in a multistage preamplifier and proposes a way to minimize the propagation delay dispersion by a non-even distribution of gain in the amplifier chain.

This paper presents a compensation structure to reduce the output common mode current of a rail-to-rail constant gm transconductance stage. The transconductance stage is a differential structure with the input transistors biased in weak inversion. This results in low power consumption and a simple relation between gm and tail currents. The constant gm is achieved by doubling the tail current in the active differential couple when the other one goes to cut off. Together with constant bias current in the output stage this can result in common mode bias current flowing from the output depending on the common mode input voltage. The proposed solution eliminates this problem by variation of the bias current in the output stage in relation to the tail currents in the differential couples. The transconductance stage was manufactured in a 0.35 um CMOS process. Measurement results are presented together with simulation data. The compensation structure cancels the common mode output currents for common mode input signals up to a frequency of 7 MHz.

This paper describes a design strategy towards a low power, DC level insensitive comparator with stable low power, level insensitive comparator with stable propagation time. The comparator b must suitable in applications were a constant propagation delay is critical, such as level crossing detection in ultrasound measurements and level crossing detection in ultrasound measurements and time quantization A/D convertem. The use of a long absolute propagation delay allows low power consumption while keeping the signal dependent propagation delay variation low. The comparator b able to process signals with all DC level within power rails due to a constant-gm, rail-to-rail, single-ended to differential converter implemented in the input stage. Schematic simulations show that the comparator has less than 1 ns delay variation at an absolute propagation delay of 12 ns. Test signals include frequencies from 0.5 MHz to 10 MHz, amplitudes fmm 30 mV to 1 V and all DC levels within rails.

Modern measurement systems can be found almost in any part of everyday life. Measurement accuracy of such systems is a vital factor which often associated with the system's overall performance and costs. The accuracy of a system is closely related to the system's power consumption. The fact that more and more of measurement systems work autonomously with limited power supply, places the power consumption issue on the same level as the issue of accuracy. The ability of a system to work long time without being adjusted (without human interference) reduces the total life time cost of the system and makes it more attractive to a potential customer. Consequently, the problems of measurement accuracy and low power consumption of electronic systems have gained a great consideration in the industry and research and there are still more findings to be made. This is necessary for the evolution technology in society. This work presents the technologies and strategies for accurate and low power measurements. Using the examples from two scientific areas (robotics and electronics), it is shown how the analysis of different error sources can produce more accurate and less expensive systems. Firstly, a new navigation system based on modern CMOS image sensors is presented. This navigation system is designed for and tested on a wheel-chair mobile robot. The strengths of such navigation systems are greater simplicity and less costs compared to laser based navigation systems. The error sources of both systems are presented and the accuracies are analyzed. Secondly, A/D conversion technology is discussed and conventional technology is compared to a new level-crossing architecture. As a result of this analysis, a building block for a level-crossing architecture is designed - a propagation delay stable comparator. The present licentiate thesis includes three scientific papers, which have contribution in the areas of robotics and electronics. The thesis specifically presents a compression algorithm that can be used in the lens distortion compensation and the design strategy with the measurement results for a propagation delay stable comparator.

Distortion introduced by a lens in a measurement system based on an image sensor usually must be compensated. The memory used for distortion compensation by a lookup table is proportional to the image sensor size. To reduce the memory usage, a compression algorithm is proposed and implemented.