Micro-controllers underlying commonplace embedded systems rely on interrupt and exception mechanisms for event driven scheduling and error handling respectively. At the lowest level of the embedded software stack, the firmware implements the actions to be taken. With outsets from the RISC-V architecture and the modern systems level programming language Rust, we seek solutions leveraging hardware accelerated interrupt and exception mechanisms while at the same time being free of non-inherent overhead - thus the title All About Nothing. The paper provides a comprehensive overview of Rust low-level code generation and identifies an implementation performance gap caused by the current design of low-level abstractions. We propose both hardware and software solutions addressing and eliminating the problem: the former by implementing an additional interrupt/exception return stack in hardware, while the latter by changing the semantics of the riscv-interrupt-m interrupt attribute. As an additional observation we find the performance gap not to be unique to Rust, the problem along with proposed solutions are equally present and applicable to C/C++ as compiled with the latest GCC toolchain targeting the RISC-V architecture.

Context switching is both a highly utilized and highly repetitive routine in interrupt-driven systems, such as safety-critical control systems. Conventional context switching routines are sequential and dependent on data memory access, which may be detrimental to time-predictability. This publication explores the use of stacked register files for efficient and predictable context switching. Two complementary microarchitectures are characterized: combinationally addressed register windowing, and a novel parallel context stack (PCS). Both implementations enable minimal latency and inherent predictability in context switching. To efficiently utilize the benefit of stacked register files while limiting hardware costs, the heterogeneous interrupt (HETI) architecture is proposed. HETI integrates a small stacked register file for accelerating a dynamically selected subset of high-priority interrupts. Automatic firmware generation is contributed to enable seamless utilization of the HETI architecture. A total of four HETI configurations on an open-source RISC-V microcontroller are evaluated against the baseline platform and an implementation of Cortex-M style hardware-assisted stacking. Implementations on a TSMC 22nm technology demonstrate low area overhead for small HETI configurations and favorable frequency characteristics against the hardware-assisted stacking implementation. A representative layout of the full system with a HETI-4 instance is presented with a gate count overhead of 1.2% and no frequency detriment in relation to the baseline design. The functional performance evaluated in a synthetic case study demonstrates how the HETI design can reduce retired instruction count by up to 26% and allow for 21% more sleep in comparison to the software baseline and Cortex-M style solution, promising significant improvements to real-time response and energy efficiency.

Low-latency, hard real time (RT) architectures require well-coordinated hardware and software implementations. The RT interrupt-driven concurrency (RTIC) framework fuses hardware-accelerated stack resource policy (SRP)-based scheduling with the memory safety of the Rust programming language, offering the state of the art in terms of overhead for Rust-based, memory-safer, multitasking RT systems. RTIC uses a thin, monolithic DSL layer to map together the Rust-language user program, the SRP programming model, and the specific hardware target implementation. However, the monolithic design of the DSL limits its scalability, leading to a similarly monolithic codebase that hinders external contributions and complicates the integration of hardware- and use-case-specific extensions. In this article, we propose an extensible implementation of RTIC for customized architectures, introducing RTIC distributions to decouple high-level functionality from platform-specific details. In addition, we present a novel technique—compilation passes—that enables syntax extension through multipass procedural macro expansions, inspired by multistage processing as implemented by contemporary compilers. We validate this approach by adding support for two new targets: the Hippomenes softcore and the Atalanta softcore, along with two custom compilation passes: one that translates deadlines into static priorities based on task set analysis and one that leverages a hardware feature to selectively accelerate critical interrupts. Our evaluation demonstrates the ways in which the proposed architecture addresses existing limitations, enhances maintainability, and provides an outset for supporting customized hardware architectures in a scalable way.

Rust is a modern systems level language with built in safety features providing strong guarantees to memory safety and defined behavior. In this paper we identify challenges and opportunities for adopting Rust in the context of safety-critical systems. In particular we focus on software safety and security requirements akin to ISO 26262, IEC 61508, and ISO/SAE 21434. We discuss Rust based development in relation to commonplace C/C++ software design and validation processes. Furthermore we compare two distinct system categories: hosted and bare-metal systems and which opportunities and challenges developers face in the context of safety and security certification in each of them.

Distributed real-time systems require end-nodes with predictable and explicitly controllable timing characteristics. Abstract timers are a promising utility to improve the realtime capability of these resource-constrained embedded systems. However, the current implementations is based on critical section access to a software priority queue, which is detrimental to the latency and time-predictability of a given system. This work explores the use of a hardware-accelerated priority queue to significantly reduce the scheduling overhead of abstract timers. A novel microarchitecture for a hardware priority queue is proposed and improves on prior work by supporting all operations, including overflow detection, with no internal latency. The proposed design is evaluated against the legacy design with application-specific integrated circuit (ASIC) synthesis targeting a 22 nm TSMC technology node. The novel microarchitecture occupies between 18 % and 25 % of the legacy design area and does not contribute to the critical path when integrated to a full microcontroller platform. A functional evaluation against software-based abstract timers demonstrates how hardware priority queues can eliminate jitter while significantly lowering the overall element access latency and program memory footprint. A proposed virtualization scheme for timer queues demonstrates how even a small hardware instance can be used to improve the real-time performance of a system.

Real-time systems are a segment of embedded systems that have remained dominated by proprietary hardware architectures, despite the continuing growth of the open-source RISC-V instruction set architecture (ISA). The introduction of core-local interrupt controller (CLIC) extensions to the RISC-V architecture presents a promising opportunity to bridge the technological gap with ARM in low-latency interrupt handling. Regarding software, the real-time interrupt-driven concurrency (RTIC) framework enables ever lighter hard real-time systems with formal compile-time guarantees for memory safety, response time and overall schedulability. In this publication we adapt Ibex, a small, open-source RISC-V processor for CLIC support and present Atalanta, a lightweight microcontroller designed around the RTIC framework. Atalanta implements a localized memory architecture that enables low-latency context switching together with a large number of supported interrupt inputs and levels provided by the CLIC specification. We evaluate Atalanta for real-time performance and implementation feasibility through simulation-based measurements and FPGA prototyping, respectively. We are able to demonstrate an interrupt latency of 5 cycles with minimal jitter and a context switch latency of 21 cycles, placing it competitively against current state-of-the-art solutions. Furthermore, we implement an FPGA prototype for the Xilinx PYNQ-Z1 and VCU118 boards, targeting a frequency of 45 MHz. We publish the sources and implementation scripts of Atalanta under a permissive open-source license.

The open RISC-V instruction set architecture (ISA) defines a new era of domain-specific computer architectures by allowing the implementation of custom, application-specific instructions. In this paper, we propose a novel approach to exposing such instructions to the end user in the Rust programming language. The proposed approach discriminates between statically known and unknown values, and automatically emits the appropriate (e.g, immediate- or register to register-type) instruction without changes to the Rust toolchain. We validate the approach by implementing a Peripheral Access Crate (PAC) for the RISC-V Real-Time Hippomenes architecture. Hippomenes introduces CSR (Control and Status Register)-mapped peripherals allowing efficient peripheral access with reduced software overhead (single instruction read-write/set/clear, including 12-bit peripheral address and optional 5-bit immediate field). Our experiments confirm that all software abstraction layers introduced are completely eliminated at compile time. Moreover, for all cases where the LLVM compiler backend can deduce values to be statically known, immediate instruction variants are selected (thus improving performance and reducing register pressure in comparison to register instructions).

Monitoring and tracing are integral to embedded systems development. In context of real-time systems, overhead is of essence as the timing behavior might be affected. In this paper we present Real-Time Monitor and Trace (RTMT) targeting (hard) real-time systems with static priority preemptive scheduling. Features of RTMT include both traditional logging capabilities, as well as event monitoring functionality. We show its feasibility to the Hippomenes FPGA implementation of the RISC-V RT architecture and demonstrate that cycle accurate time stamping of interrupt entry/exit and resource locking/unlocking is possible with zero interference to the running application. Logging, on the other hand comes with constant time overhead and is guaranteed to be non-blocking. RTMT builds on Nested COBS (N-COBS), a novel extension of the COBS protocol allowing for static priority preemptive framing with single byte overhead. In the paper we present the N-COBS protocol, formalize and prove its key properties: protocol soundness, encoder/decoder reversibility and single byte overhead. Design simplicity is demonstrated by the provided System Verilog encoder implementation as used to showcase monitoring and tracing of Rust RTIC applications running on the RISC-V RT architecture.

The RTIC framework, based on Stack Resource Policy (SRP) scheduling, ensures correctness by construction, single-stack execution, and race- and deadlock-free operation with bounded priority inversion. Unlike typical concurrency frameworks/RTOSes, which expose APIs through data structures and functions, RTIC is a DSL implemented as a Rust procedural macro. This macro-based design however, limits the modularity and scalability, resulting in a monolithic codebase that restricts external contributions and hampers support for target- or use-case-specific extensions. This paper proposes a modular approach to RTIC, introducing RTIC distributions to decouple high-level functionality from lowlevel hardware-specific details. Additionally, we present a novel techniquemd—Compilation Passes—that enables modular syntax extensions through multi-pass Rust procedural macro expansions, inspired by compiler multi-stage processing. We validate this approach by adding support for a new target (the RISC-V RT-based Hippomenes soft-core) and a compilation pass that translates deadlines into static priorities based on task set analysis. Our evaluation demonstrates that the proposed architecture successfully addresses existing limitations and enhances both maintainability and agile development.