This article presents the HAS-16T static random access memory (SRAM) cell, a novel 16-transistor design implemented in 45 nm CMOS technology to achieve robust security against side-channel attacks (SCAs) and fault injection attacks (FIAs). The cell integrates sleep transistors, loop-cut mechanisms, prewrite conditioning, and an inverter feedback loop to mitigate leakage power analysis (LPA), timing analysis attacks (TAAs), and FIAs. A comprehensive security measure, based on Monte Carlo simulations (1000 samples, 1 V, 27 ∘ C), quantifies resistance through histogram overlap and failure probability, yielding a total security matrix (SMTotal) of 98.68%, the highest among evaluated cells (e.g., 6T: 38.37%, EQ-14T: 68.91%). Simulations in the Cadence design environment reveal the HAS-16T’s second-highest static noise margin (SNM), moderate read/write delays, second-lowest write dynamic power, and second-highest leakage power, reflecting a balanced tradeoff for security-critical applications. Compared to conventional and secure SRAM designs, the HAS-16T offers unparalleled protection, making it ideal for cryptographic and embedded systems. Future work includes area optimization and scalability to advanced process nodes.

Conventional N-curve SRAM stability metrics—static voltage noise margin (SVNM), static current noise margin (SINM), write-trip voltage (WTV) and write-trip current—are extracted from zero crossings or current extrema of the storage-node 𝑉–𝐼 trace. They can under-report low-voltage stability loss when the N-curve current amplitude decreases more rapidly than its zero-crossing separation, approaching exponential dependence as the critical devices enter weak inversion. This letter introduces two area-integrated indicators, static integrated noise margin (SENM) and write-trip integral, together with bistability collapse voltage and noise charge margin as complementary robustness indicators. To first order, SENM ∝SVNM ·SINM, so SENM captures the joint 𝑉–𝐼 degradation not visible from SVNM alone. Post-layout simulation of a 45 nm 6T cell shows that scaling 𝑉DD from 1.0 to 0.4 V decreases SVNM by 79.0% but SENM by 98.4%; across process corners at 0.6 V, SENM spans 12.3 × versus 1.6 × for SVNM. A 1000-point Monte Carlo yields 𝜇/𝜎 =8.22 for SENM, comparable to SVNM and above the current-domain and writeability metrics. The framework complements, not replaces, conventional N-curve analysis.

Electronic waste (e-waste) is among the fastest-growing global waste streams, with 62 million tonnes generated in 2022 and only 22.3% formally recycled, while generation is projected to reach 82 million tonnes by 2030. Fragmented record-keeping, weak chain-of-custody controls, and limited transparency enable illegal dumping, fraudulent recycling claims, and loss of recoverable materials. This paper presents a narrative literature review of blockchain and distributed ledger technologies applied to electronics and e-waste management. Following a structured search and relevance screening of major scientific databases, publisher platforms and grey literature (last search was run on 15 July 2026), 110 sources published between 2017 and 2026 were thematically synthesized across four domains: technological developments, sustainability and circular-economy implications, traceability and compliance mechanisms, and e-waste management applications. Blockchain delivers value primarily through an auditable chain-of-custody built on three pillars: standardized item and batch identities, standardized lifecycle event schemas, and licensed-actor attestations supported by off-chain evidence anchored on-chain. Recurring design patterns include permissioned consortium networks, hybrid storage, and role-based access control. Persistent barriers include data-input integrity, scalability, governance, and cost. Blockchain immutability protects stored records but cannot correct falsified inputs, making trusted data capture and governance the decisive factors for reliability. Adoption should be evaluated against measurable indicators, such as traceability completeness, audit-time reduction, fraud rates, and verified material recovery, rather than assumed benefits.

Static random access memory (SRAM) faces significant reliability challenges in radiation-prone environments, as high-energy particles can induce single-event upsets (SEUs) by disrupting stored data at sensitive nodes. In this work, we aim to design a radiation-hardened SRAM cell that can withstand harsh radiation environments in space. In order to design the DFRH_14T SRAM cells, we utilised two feedback mechanisms. Firstly, we used two crossed coupled latches with an interlocked connection, which creates positive feedback and restores the affected node value. The second method involved using two PMOS transistors controlled by a word-line signal. These transistors connect their drain and source to the internal stored nodes, generating positive feedback. Both feedback machines enable the system to withstand increased radiation levels. Additionally, in hold mode, its beta value is increasing, which helps to improve the hold noise margin. Drives by two transistors make write and read operations faster, which helps to reduce read and write delay. We address the HALF selection issue, by implemented a divided word line, which significantly enhanced the WL driving strength. 

Small centrifugal pumps, critical for rural and peri-urban water supply, often lack advanced monitoring. This study develops a low-cost operational Digital Twin (DT) for a 3.7 kW induction motor-driven pump at IIIT-Hyderabad (IIIT-H), optimised for resource-constrained settings with limited bandwidth and power. Using an ESP32 gateway, temperature, current, and vibration data are streamed to ThingSpeak, stored in MongoDB, and synchronised with a Simulink model via Eclipse Ditto. The system continuously compares simulated and actual pump data and raises alerts when abnormal behaviour is detected using a Root Mean Square Error (RMSE)-based anomaly detector. A dashboard was developed to enable remote motor operation and automated shutdown during unsafe conditions. The twin operates in a partially closed-loop mode: sensor streams continuously update the virtual model and generate alerts, while relay-based actuation enables automated start/stop motor operation. From August to November 2024, 160,000 minutely sampled records demonstrated an ≈8 -second end-to-end latency, which is characterised as near real-time and adequate for supervisory pump monitoring. This performance meets SCADA real-time standards, with a modelling error of approximately 5%. The system enabled anomaly detection, identifying faults hours in advance without labelled data, and achieved rapid operator adoption with minimal training. This open-source solution bridges a research gap for 3-5 HP pumps, offering a scalable blueprint for small utilities and supporting future enhancements like fully closed-loop control.

This study reports, for the first time, the fully additive fabrication of miniaturized, embedded triple-stacked copper spiral inductors—an unprecedented achievement in multilayer inductor manufacturing. Using our novel Sequential Build-Up–Covalent Bonded Metallization (SBU–CBM) method, we demonstrate a etch-free, room-temperature process capable of producing complex 3D inductor architectures with sub-10 μm features and high vertical integration. Unlike conventional additive, subtractive or hybrid subtractive–additive techniques, the SBU–CBM method enables high-resolution laser-defined patterning, selective electroless copper deposition, and accurate optical alignment— eliminating the need for vacuum systems, chemical etching, or thermal sintering. The successful fabrication of three vertically interconnected spiral inductors through 10 μm copper microvias confirms the method’s unmatched capability in fabricating intricate multilayer geometries through a fully additive process. Optical microscopy and X-ray Computed Tomography (XCT) imaging validates the structural integrity, precise interlayer alignment, and continuous electrical connectivity across all layers. Critically, the method achieves uniform miniaturized copper strip widths of 10 μm, underscoring its strength in high-density packaging and next-generation integrated systems. This breakthrough establishes SBU–CBM as a transformative approach for realizing compact, high-performance, and scalable 3D embedded components in future electronic applications.

This study investigates the presence and potential removal of metal particles that exist in fibers obtained from recycled coated and printed paper, which must be removed through deinking and washing to ensure material safety and optimize pulp formulation for use in food and pharmaceutical packaging applications. For the production of modern packaging material, virgin cellulose fibers are combined with recycled fibers. In such a pulp mixture, recycled fibers introduce sticky particles that contain binders, metals, and ink particles. Those sticky particles that induce aggregation of residues and fibers alter pulp rheology and hinder product formation; therefore, their removal during the deinking process is essential to ensure pulp quality, process efficiency, and product viability. Recycled coated paper was pulped and deinked using a conventional washing process, and the metal content in cellulose pulp was evaluated with Inductively Coupled Plasma Mass Spectrometry (ICP-MS). Rheological measurements were used to reveal its effect on the flow behavior of pulp. The results indicate that the amount of coating with the presence of adhesives and the electronegativity of metals affects metal separation upon washing and deinking. Metals with lower electronegativity, such as Ag, Ti, Cr, V, and Zn, are easily removed from pulp after washing, improving the rheological behaviour of pulp. This research provides novel insights into optimizing the composition and processing of recycled pulp to enhance sustainability, safety, and quality in sustainable packaging production.

This work is based on the design of an SRAM memory array for on board satellite image compression systems, including memory size, cost, power efficiency, and vulnerability to single event upsets (SEU). Initially, we designed a memory cell, RH_14T, specifically to mitigate the impact of SEUs. Subsequently, we incorporated RH_14T into the on-board memory array in two variations: RH_14T with minimal area overhead (RH_14T_small) and RH_14T with substantial area overhead (RH_14T_large), which have critical charges of 30.10 and 38.77 fC, respectively. Given the higher sensitivity of higher order bits compared to lower order bits in image pixels, RH_14T_small was allocated for the least significant bit (LSB) positions. RH_14_large, on the other hand, was used for the most significant bit (MSB) positions within the memory array. This configuration enhanced the array's overall area, power, and space radiation tolerance. Furthermore, the RH_14T model was bench marked against other recently introduced radiation-hardened SRAM cells and compared proposed RH_14T CC18T, RHC14T, RHMC12T, SARP12T, SRRD12T, DICE, and QUCCE12T across several critical design parameters. Notably, RH_14T's sensitive nodes can recover their original data even after radiation-induced value flips. In addition to these benefits, RH_14T also demonstrates a high static voltage noise margin and reduced read and write delays compared to most of the cells it was compared with. 

This semi-systematic review paper discusses four research questions based on findings from the last 10 years: What are the crucial issues in the ongoing debate on the development of the electric vehicle (EV) concept? Where are the major conflicting points and focuses between sustainable economy and EVs? How does the mining of metals and minerals follow current zero-waste sustainability trends, and how does the prediction of the magnitude of the future demand for EV batteries guide strategic decision-making in policies throughout the globe? As it is not easy to currently predict how metals necessary for EV productions will be produced, this article suggests a strategy that is diverse regarding its approaches to shaping the sustainable mining and further development of EVs, along with the involvement of urban planning. Using broad literature and a published pool of prediction scenarios, we provide a comprehensive assessment of future EV battery raw materials development under a range of scenarios, accounting for factors such as developments in battery technology, variations in the EV fleet composition, sustainability aspects of development of second use and recycling technologies. Additionally, this paper demonstrates how blockchain technology is likely to force mineral and metal supply chains to become significantly more traceable and transparent.

The development of miniaturized embedded inductors holds crucial significance in advancing modern electronic devices, contributing to their size reduction, enhanced efficiency, and improved performance. This study introduces a groundbreaking, fully additive manufacturing process designed for fabricating miniaturized embedded double-stacked copper spiral inductors. The Sequential Build Up-Covalent Bonded Metallization (SBU-CBM) method serves as the foundation for this novel approach. The experimental process evolves in three stages. In Stage I, the first layer of polyurethane (PU1) is initially spin-coated onto the FR-4 base substrate. The lower embedded copper spiral inductor is then fabricated on top of PU1, employing the SBU-CBM method. Moving to Stage II, the second layer of polyurethane (PU2) is spin-coated onto the existing PU1 layer. Subsequently, a single microvia is created and copper-plated using the SBU-CBM method, establishing a crucial vertical connection between the upper and lower embedded copper spiral inductors. Finally, Stage III involves the fabrication of the upper embedded copper spiral inductor on PU2, utilizing the SBU-CBM method. Optical microscopy and X-ray Computed Tomography (XCT) images confirm the successful formation of embedded double-stacked copper spiral inductors, a configuration where two embedded copper spiral inductors are interconnected through a copper microvia. Notably, the copper strip lines within the spiral inductor configuration are miniaturized to a width of 10 μm, while the diameter of the microvias is reduced to 10 μm, indicating the miniaturization precision achieved through this novel additive manufacturing process.