This work is based on the design of an SRAM memory array for on board satellite image compression systems, including memory size, cost, power efficiency, and vulnerability to single event upsets (SEU). Initially, we designed a memory cell, RH_14T, specifically to mitigate the impact of SEUs. Subsequently, we incorporated RH_14T into the on-board memory array in two variations: RH_14T with minimal area overhead (RH_14T_small) and RH_14T with substantial area overhead (RH_14T_large), which have critical charges of 30.10 and 38.77 fC, respectively. Given the higher sensitivity of higher order bits compared to lower order bits in image pixels, RH_14T_small was allocated for the least significant bit (LSB) positions. RH_14_large, on the other hand, was used for the most significant bit (MSB) positions within the memory array. This configuration enhanced the array's overall area, power, and space radiation tolerance. Furthermore, the RH_14T model was bench marked against other recently introduced radiation-hardened SRAM cells and compared proposed RH_14T CC18T, RHC14T, RHMC12T, SARP12T, SRRD12T, DICE, and QUCCE12T across several critical design parameters. Notably, RH_14T's sensitive nodes can recover their original data even after radiation-induced value flips. In addition to these benefits, RH_14T also demonstrates a high static voltage noise margin and reduced read and write delays compared to most of the cells it was compared with.