Industrial automation is facing challenges related to a manufacturing change from mass pro-duction to mass customization. As a result, the focus of automation has been shifting to flexi-bility, reconfigurability and safety assurance resulting in a new class of systems that is heavilymodular. We call this new class of systems as Component-Based industrial Automation Sys-tems (CBAS).

Given the current challenges and shift in focus, the current engineering practices and meth-ods need to be changed or upgraded. One of these practices is software verification and valida-tion (V&V) techniques. Simulation is one of the well-known V&V techniques used currentlyin CBAS. Simulation is performed by building simulation models for the physical process,for example, simulation using Matlab. However, development of simulation models is time-consuming and does not guarantee 100% validation of the automation control software makingjust simulation inadequate for CBAS. To address this problem, formal verification has beenconsidered as a proper complementary V&V technique. Discrete state model checking is oneof such approaches, which is the process of automatically verifying whether a set of desiredformal specifications is satisfied over the target system model. While model checking is com-putationally resource hungry, it has been successfully used in other adjacent areas of computersystems engineering, such as hardware design, proving its ability to handle problems of rea-sonably large complexity. This suggests that model checking can be applied in the industrialautomation domain, and there has been an impressive number of works towards this goal.

Despite moderate successes and promises the reality is that formal techniques are rarelyused in the development practice by industrial automation engineers. It seems that the existingtools and methods do not fit into the current Software Development Life Cycle (SDLC) of au-tomation systems engineering. This thesis first looks at current state of art with comprehensiveliterature review, identifying 3 main challenges for lack of industrial adoption of formal verifi-cation. The thesis then presents various formal method approaches to address these challenges.The main contribution of the thesis is a method for the formal verification of IEC 61499 func-tion block applications using Abstract State Machines (ASM) and model checking. A formaldescription for main artifacts of the standard is presented in the thesis. Further, ASM rules fortranslation for function blocks to the input format of the SMV model checker is presented. Inthis way, the proposed verification method enables the formal verification of the IEC 61499control systems.

As results, the thesis presents an application of this framework to industrial automation usecases to check for functional and non-functional requirements. It also presents use cases wherethe proposed framework is used for verifying portability of IEC 61499 based control applica-tions across different implementation platforms compliant with the IEC 61499 standard.