Monitoring and tracing are integral to embedded systems development. In context of real-time systems, overhead is of essence as the timing behavior might be affected. In this paper we present Real-Time Monitor and Trace (RTMT) targeting (hard) real-time systems with static priority preemptive scheduling. Features of RTMT include both traditional logging capabilities, as well as event monitoring functionality. We show its feasibility to the Hippomenes FPGA implementation of the RISC-V RT architecture and demonstrate that cycle accurate time stamping of interrupt entry/exit and resource locking/unlocking is possible with zero interference to the running application. Logging, on the other hand comes with constant time overhead and is guaranteed to be non-blocking. RTMT builds on Nested COBS (N-COBS), a novel extension of the COBS protocol allowing for static priority preemptive framing with single byte overhead. In the paper we present the N-COBS protocol, formalize and prove its key properties: protocol soundness, encoder/decoder reversibility and single byte overhead. Design simplicity is demonstrated by the provided System Verilog encoder implementation as used to showcase monitoring and tracing of Rust RTIC applications running on the RISC-V RT architecture.