Low-latency, hard real time (RT) architectures require well-coordinated hardware and software implementations. The RT interrupt-driven concurrency (RTIC) framework fuses hardware-accelerated stack resource policy (SRP)-based scheduling with the memory safety of the Rust programming language, offering the state of the art in terms of overhead for Rust-based, memory-safer, multitasking RT systems. RTIC uses a thin, monolithic DSL layer to map together the Rust-language user program, the SRP programming model, and the specific hardware target implementation. However, the monolithic design of the DSL limits its scalability, leading to a similarly monolithic codebase that hinders external contributions and complicates the integration of hardware- and use-case-specific extensions. In this article, we propose an extensible implementation of RTIC for customized architectures, introducing RTIC distributions to decouple high-level functionality from platform-specific details. In addition, we present a novel technique—compilation passes—that enables syntax extension through multipass procedural macro expansions, inspired by multistage processing as implemented by contemporary compilers. We validate this approach by adding support for two new targets: the Hippomenes softcore and the Atalanta softcore, along with two custom compilation passes: one that translates deadlines into static priorities based on task set analysis and one that leverages a hardware feature to selectively accelerate critical interrupts. Our evaluation demonstrates the ways in which the proposed architecture addresses existing limitations, enhances maintainability, and provides an outset for supporting customized hardware architectures in a scalable way.